STW81200 datasheet(28/58 Pages) STMICROELECTRONICS

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Circuit description

STW81200

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DocID025943 Rev 7

Figure 30. PFD diagram

7.5

Lock detect

The lock detector indicates the lock state for the PLL. The lock condition is detected by

comparing the UP and DOWN outputs of the digital Phase Frequency Detector

A CMOS logic output signal indicates the lock state; the polarity of the output signal can be

inverted using the LD_ACTIVELOW bit.

The lock condition occurs when the delay between the edges of UP and DOWN signals is

lower than a specific value (3-bit programmable from 2 ns to 16 ns) and this condition is

stable for a specific number of consecutive PFD cycles (3-bit programmable counter from 4

to 4096 cycles).

This flexibility is needed by the lock detector circuitry to work properly with all the possible

different PLL setups (Integer-N, Fractional-N, different PFD frequencies and so on).

7.6

Charge pump

This block drives two matched current sources, Iup and Idown, which are controlled

respectively by the UP and DOWN PFD outputs. The nominal value of the output current

(ICP) can be set by a 5-bit word.

The minimum value of the output current (ICP) is 158 µA.

The charge pump also includes a compensation circuit to take into account the KVCO

variation versus VCO control voltage, which changes with temperature and process for a

specified frequency. The KVCO compensation block adjusts the nominal ICP value,

minimizing the variation of the product ICP x KVCO to keep the PLL bandwidth constant for

the specified frequency.

In order to compensate the change of KVCO over frequency, the user should manually adjust

the ICP value to keep the PLL bandwidth constant.

In addition, the charge-pump output stage can operate with a 2.5 V to 5.0 V supply voltage.

The LDO_4V5 regulator, programmable at 2.6 V, 3.3 V and 4.5 V, can be used for this

purpose. The CP_SUPPLY_MODE[1:0] field (ST4 Register) must be set according to the

supply voltage.

Down

ABL

Delay

DFF

VDD

Fref

VDD

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