STW81200 datasheet(16/58 Pages) STMICROELECTRONICS

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Electrical specifications

STW81200

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DocID025943 Rev 7

PLL miscellaneous

IPLL

PLL current

Consumption(8)

Prescaler, digital dividers, misc.

IDSM

ΔΣ Modulator current

consumption(8)

3.5

1. The maximum frequency of the Reference Divider is 200 MHz; when using higher reference clock frequency (up to the

max. value of 800 MHz) the internal divider by 2 or divider by 4 must be enabled.

The fractional mode is allowed in the full frequency range only with reference clock frequency >11.93 MHz

With reference clock frequency in the range 10 MHz to 11.93 MHz, due to the limits of N value in fractional mode, the full

VCO frequencies would not be addressed in fractional mode; in this case the frequency doubler in the reference path can

be enabled.

2. Reference clock signal @ 100 MHz, R=2

3. The minimum frequency step is obtained as FPFD / (2^21); these typical values are obtained considering FPFD = 100 MHz.

4. PFD frequency leakage.

5. This is the level inside the PLL loop bandwidth due to the contribution of the

ΔΣ Modulator. In order to obtain the fractional

spurs level for a specific frequency offset, the attenuation provided by the loop filter at such offset should be subtracted.

6. Once a VCO is programmed at the initial temperature T0 inside the operating temperature range (-40 °C to +85 °C), the

synthesizer is able to maintain the lock status only if the temperature drift (in either direction) is within the limit specified by

ΔTLK, provided that the final temperature Tf is still inside the nominal range.

7. In order to guarantee the performance of

ΔTLK the bit CAL_TEMP_COMP in register ST6 must be set to ‘1’.

8. Current consumption measured with PLL locked in following conditions: Reference clock signal @ 100 MHz; PFD

@50 MHz (R=2); VCO @ 4005 MHz

Table 6. Electrical specifications (continued)

Symbol

Parameter

Condition

Min

Typ

Max

Units

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