AM79C875KC datasheet(10/48 Pages) AMD

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Am79C875

PIN DESCRIPTIONS

Media Connections

TX[3:0]±

Transmit Output

Output

The TX[3:0]± pins are the differential transmit output

pairs. The TX[3:0]± pins transmit 10BASE-T or MLT-3

signals depending on the state of the link of the port.

RX[3:0]±

Receive Input

Input

The RX[3:0]± pins are the differential receive input

pairs. The RX[3:0]± pins can receive 10BASE-T or

MLT-3 signals depending on the state of the link of the

port.

100BASE-FX Function/Test

SDI+/TEST[0]

Signal Detect Input+

(For Port 3 only)

Analog Input/Output

This pin indicates signal quality status on the fiber-optic

link in 100BASE-FX mode. When the signal quality is

good, the SDI+ pin should be driven high relative to the

SDI- pin. 100BASE-FX is disabled when both pins are

simultaneously pulled low. SDI- can also be used for

Signal Detect Common Mode Voltage input.

When in test mode, SDI+, SDI-, FXR+, and FXR- pins

are used as TEST[3:0].

SDI-/TEST[1]

Signal Detect Input-

(For Port 3 only)

Analog Input/Output

This pin indicates signal quality status on the fiber-optic

link in 100BASE-FX mode. When the signal quality is

good, the SDI+ pin should be driven high relative to the

SDI- pin. 100BASE-FX is disabled when both pins are

simultaneously pulled low. SDI- can also be used for

Signal Detect Common Mode Voltage input.

When in test mode, SDI+, SDI-, FXR+, and FXR- pins

are used as TEST[3:0].

FXR+/TEST[2]

Fiber Receive Input

(For Port 3 only)

Analog Input/Output

When Port 3 is configured as FX Channel, FXR± are

ECL level FX receive pins.

When in test mode, SDI±, and FXR± pins are used as

TEST[3:0].

FXR-/TEST[3]

Fiber Receive Input

(For Port 3 only)

Analog Input/Output

When Port 3 is configured as FX Channel, FXR± are

ECL level FX receive pins.

When in test mode, SDI+, SDI-, FXR+, FXR- pins are

used as TEST[3:0].

FXT±

Fiber Transmit Output

(For Port 3 only)

Analog Output

When Port 3 is configured as FX Channel, FXT± are

ECL level FX transmit pins.

Clock

REFCLK

Reference Clock Input Signal

Input

The REFCLK pin is the reference clock input. The

REFCLK signal must be a 50-MHz signal.

RMII Signals

TXD[3:0]_[1:0]

RMII TXD for Ports 0 to 3

Input

These pins are the transmit data input to the RMII of

Ports 0:3.

TX_EN[3:0]

RMII Transmit Enable

Input

These pins are the transmit enable inputs to the RMII.

RXD[3:0]_[1:0]

RMII Receive Data for Ports 0 to 3

Output

These pins are the receive data for Port 0:3.

RX_ER[2:0]

RMII Receive Error for Ports 0 to 2

Output

These pins indicate receive errors for the correspond-

ing por t. The pin goes HIGH whenever the

corresponding receiver detects a symbol error.

RX_ER[3]/PHYAD_ST

RMII Receive Error for Port 3

Input/Output

PHY Address Shift

This pin indicates receive errors for Port 3. It goes

HIGH when the corresponding receiver detects a

symbol error.

At power up, this pin is used to set the PHY address by

increasing it by 1. If it is HIGH at power up, the PHYAD

of each port is the upper-3 bits and the port number for

the lower-2 bits. If it is LOW, the PHYAD is incremented

by 1. For example, if the pin is HIGH at power-up and

the upper-3 bits are set to 000, the PHYAD of each port

(in binary notation) is 00000, 00001, 00010, 00011 re-

spectively. If the pin is LOW at power-up and the upper-

3 bits are set to 000, the PHYAD of each port is 00001,

00010, 00011, and 00100, respectively. This allows a

method of avoiding setting an address to 00000, which

could cause problems with some MACs.

CRS_DV[3:0]

Carrier Sense/Data Valid

Input/Output, Pull-Down

The CRS_DV pin is asserted high when media is

non-idle.

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