AM79C875KC datasheet(26/48 Pages) AMD

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Am79C875

MII Management Control Register (Register 0)

Table 7.

Reg

Bit

Name

Description

Read/

Write

Default

Reset

1 = PHY reset.

0 = Normal operation.

This bit is self-clearing.

RW/SC

Loopback

1 = Enable loopback mode. This will loopback TXD to RXD,

thus it will ignore all the activity on the cable media.

0 = Disable loopback mode. Normal operation.

Speed Select

1 = 100 Mbps.

0 = 10 Mbps.

Set by

FORCE100

Auto-Neg Enable

1 = Enable Auto-Negotiation process (overrides 0.13 and 0.8).

0 = Disable Auto-Negotiation process.

Set by

ANEGA pin

Power Down

1 = Power down. The NetPHY™ 4LP device will shut off all

blocks except for MDIO/MDC interface.

0 = Normal operation.

Isolate

1 = Electrically isolate the PHY from MII. However, PHY is still

able to respond to MDC/MDIO.

0 = Normal operation.

Restart

Auto-Negotiation

1 = Restart Auto-Negotiation process.

0 = Normal operation.

RW/SC

Duplex Mode

1 = Full duplex.

0 = Half duplex.

Auto-Negotiation enabled: This bit is writable but will be

ignored.

Auto-Negotiation disabled: This pin is reset read value of

DPLX.

Set by

DPLX pin

Collision Test

1 = Enable collision test, which issues the COL signal in

response to the assertion of TX_EN signal. Collision test is

enabled regardless of the duplex mode.

0 = disable COL test.

6:0

Reserved

Write as 0, ignore on read.

MII Management Control Register (Register 0)

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