PC87415VCG datasheet(11/42 Pages) NSC

11 / 42 page

50 Configuration Registers (Continued)

Reg

Description

(HEX)

40 – 42

CONTROL REGISTER (CTRL)

Default value is 00000000h (after Reset)

Bit 0 Reserved

Bit 1 0 (Always) Reserved

Bit 2 0 e Software reset to CH1CH2 off

1 e Software reset to CH1CH2 on

Bit 3 0 e IDE

PWR set on

1 e IDE

PWR set off

Note

Bit 18 must be set to ‘‘1’’ to allow Bit 3 to toggle IDE

PWR

B18

IDE

PWR

1 (Default at power up reset)

1 (IDE

PWR set to on)

0 (IDE

PWR set to off)

( ) Asserted for t

25 s

Bit 4 0 e Map CH1

INT according to legacynative mapping scheme

1 e Map CH1

INT to INTA regardless if in legacy mode

Bit 5 0 e Map CH2

INT according to legacynative mapping scheme

1 e Map CH2

INT to INTA regardless if in legacy mode

Bit 6 0 e INTA

unmasked

1 e INTA

masked

Bit 7 0 e Write to vendor ID and device ID registers disabled

1 e Write to vendor ID and device ID registers enabled

Bit 8 0 e Channel 1 interrupt unmasked

1 e Channel 1 interrupt masked

Bit 9 0 e Channel 2 interrupt unmasked

1 e Channel 2 interrupt masked

Bit 10 0 e PCI Base Address Register 2 and 3 enabled

1 e PCI Base Address Register 2 and 3 disabled

Bit 11 0 e PCI data phase WATCHDOGTM timer disabled

1 e PCI data phase WATCHDOG timer enabled

http

www nationalcom

PC87415VCG bảng dữ liệu(PDF) 11 Page - National Semiconductor (TI)

PC87415VCG bảng dữ liệu(HTML) 11 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

bảng dữ liệu tải về

Link URL