PC87415VCG datasheet(25/42 Pages) NSC

25 / 42 page

70 Functional Description (Continued)

The Memory Region specified by the descriptor cannot

cross a 64k memory boundary The Memory Region Physi-

cal Base Address is aligned on a 2 byte boundary

741 DMA Engine

The built-in DMA controller supports 2 channels and each

channel can operate independently The descriptors are

memory resident and are read every time a transfer takes

place The DMA engine is used to initiate and carry out data

transfers between the IDE device and system memory Sep-

arate command and status registers are used per channel

allowing both channels to time share the DMA engine if both

channels need to transfer data When bus master IDE is

enabled on a channel that channel’s write and prefetch

buffers are used to either post or prefetch data tofrom the

disk When two channels are requesting DMA services from

the DMA engine then after the first request is serviced by

completing the entire transfer (EOT e 1 and byte count e

0) the second channel begins the transfer

Figure 4 below

shows the DMA block

TLF12497 – 11

FIGURE 4 DMA Block

7411 Alignment

The device will transfer data tofrom memory in double

word (4 bytes) transfers If the Memory Physical Region

Base Address is double word aligned and the Byte count is

double word aligned then the transfer will be double words

on the PCI bus using the PCI burst cycle If either the Memo-

ry Physical Region Base Address or the Bytes count are not

double word aligned the PC87415 will still transfer double

words on the PCI bus This would be a failure condition The

software program needs to ensure that the Memory Physi-

cal Region Base Address and Byte count both be double

word aligned

742 DMA Engine Protocol

The DMA engine works together with the prefetch buffers

and the write buffers to optimize IDE transfers and minimize

PCI bus utilization The following sections show how the

DMA engine behaves under three different scenarios

7421 Scenario 1

The device request the bus and no one else is on the bus

(the bus is idle) No other masters are requesting the bus

throughout the entire transfer of a sector

74211 Bus Master Writes

The device arbitrates for the PCI bus and at the same time

begins reading the data from the drive and filling the pre-

fetch buffers After the bus is granted the device reads the

descriptor from memory loads the address pointer and byte

count and then gets off the PCI bus (if the prefetch buffer is

not half full) When the prefetch buffer is half full the device

arbitrates onto the PCI bus (if not on the bus yet) and when

granted starts writing out the prefetched data (2 DWords)

out onto the PCI bus while prefetching data from the IDE

drive When the prefetch buffer is empty the device relin-

quishes the bus If it wasn’t the last descriptor (EOT is 0) the

device continues prefetching from the drive while reading

the new descriptor from memory

Figure 5 shows the DMA

flow The total PCI bus utilization for this type of transfer can

be calculated by the following equation

PCI Bus Utilization e ARB a Read Descriptor

256

ARB a Tw a Twb

Where

ARB e number of clocks for arbitration

Read Descriptor e number of clocks to read the descriptor

Tw e number of clocks for first non burst write

Twb e number of clocks for burst write

TLF12497 – 30

FIGURE 5 Bus Master WritesScenario 1

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