PC87415VCG datasheet(27/42 Pages) NSC

27 / 42 page

70 Functional Description (Continued)

74222 Bus Master Reads

The device arbitrates onto the bus and waits for a grant

When the bus is granted the device reads the descriptor

from system memory and loads the address pointer and

byte count It then begins to read data from system memory

and buffering it in the posted write buffers until the buffer is

full When the FIFO is full the device releases the PCI bus

When the device sees data in the buffer it begins to write to

the drive The device will request the PCI bus whenever the

posted write buffer is either empty or half full If the posted

write buffer is empty (initial condition or due to another mas-

ter on the PCI bus interrupting the transfer) then the device

reads in 4 Dwords from memory filling the buffers If the

posted write buffer is half full then the device reads in 2

Dwords from memory filling the buffers If another device

becomes a bus master while reading from memory the de-

vice will continue to write data to the drive emptying the

write buffers The device continues to request the PCI bus if

the byte count is 0 and EOT e 0 and the buffer is empty

When it receives a grant the device bursts in data (4

Dwords) into the write buffer until it is full When the byte

count is 0 and it was the last descriptor (EOT is 1) the

device relinquishes the bus while the write buffers are being

emptied out onto the IDE bus If it wasn’t the last descriptor

(EOT is 0) the device reads the new descriptor from memo-

ry while the device is writing out to the drive the contents of

the write buffers

Figure 8 shows the DMA flow

TLF12497 – 33

FIGURE 8 Bus Master ReadsScenario 2

7423 Scenario 3

The device requests the bus while another master started a

bus transaction While the transfer takes place another

master requests the bus The latency timer is set to 2 ms

74231 Bus Master Writes

The device arbitrates for the PCI bus and at the same time

begins reading the data from the drive and filling the pre-

fetch buffers The device waits until the other master com-

pletes and the bus is granted After the bus is granted the

device reads the descriptor from memory loads the address

pointer and byte count and then starts writing out the pre-

fetched data out onto the PCI bus (4 Dwords) The device

will request the PCI bus everytime the prefetch buffer is

either half full or full When the prefetch buffer is half full

then the device will write out 2 Dwords to memory When

the prefetch buffer is full (due to another master owning the

PCI bus) then the device will write out 4 Dwords to memory

If another device becomes a master while the device is writ-

ing out to memory the device will continue to prefetch data

from the drive until the prefetch buffers are full at which time

it stops prefetching The device continues to request the

bus if the prefetch buffer is full When it receives a grant the

device writes out the data (4 Dwords) from the prefetch buff-

ers until the byte count is 0 When the byte count is 0 and it

was the last descriptor (EOT is 1) the device relinquishes

the bus If it wasn’t the last descriptor (EOT is 0) the device

continues prefetching from the drive while reading the new

descriptor from memory

Figure 9 shows the DMA flow

TLF12497 – 34

FIGURE 9 Bus Master WritesScenario 3

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