PC87415VCG datasheet(30/42 Pages) NSC

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70 Functional Description (Continued)

7453 Byte Count is Greater Than IDE Transfer Size

When the Byte Count is programmed to be greater than the

IDE transfer size an IDE interrupt will be received by the

device but will be blocked because Byte Count is not 0 The

software will time out because it has not received any inter-

rupt It will then read the status register and will see the

Channel x Interrupt bit set and the Channel x Active bit set

7454 Transfer in Progress

When the software reads the status register of the device

while the DMA is in progress it will read Channel x Interrupt

bit not set and the Channel x Active bit set

746 Bus Master Programming Sequence

To initiate a bus master transfer between memory and an

IDE DMA slave device the following steps are required

1 Software prepares a PRD table in system memory Each

PRD is 8 bytes long and consists of an address pointer

to the starting address and transfer count of the memory

buffer to be transferred In any given PRD table two con-

secutive PRDs are offset by 8 bytes and are aligned on a

4-byte boundary

2 Software provides the starting address of the PRD table

by loading the PRD table pointer register The direction

of the data transfer is specified by setting the Read

Write Control bit in the Bus Master IDE Command regis-

ter for the appropriate channel Clear the Interrupt and

Error bits in the Bus Master IDE Status register for the

appropriate channel

3 Software issues the appropriate DMA transfer command

to the disk device

4 Engage the bus master function by writing a one to the

Start bit in the Bus Master IDE Command register for the

appropriate channel

5 The device arbitrates onto the PCI bus and gets ready to

transfer

6 When the bus is granted the device reads one entry of

the Physical Region Descriptor table pointed by the

Physical Region Descriptor Table Address

7 The device transfers data tofrom memory pointed by

the Memory Region Physical Base Address responding

to DMARQ from the IDE device

8 Transfers continue until the byte count is 0 from the last

Physical Region Descriptor (EOT is set to 1) at which

time the devices relinquishes ownership of the PCI bus

9 At the end of the transfer the IDE drive signals an inter-

rupt

10 In response to the interrupt software reads the device

Status register and the drive status to determine if the

transfer completed successfully and then resets the

StartStop bit in the command register

Figure 11 shows an example of a link list DMA transfer In

the example below channel 1 transfers data between 3

memory regions and channel 2 transfers between 2 memo-

ry regions Each memory region could hold either a single

sector or multiple sectors depending on the byte count of

each memory region

TLF12497 – 18

FIGURE 11 Link List Example

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