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PC87415VCG bảng dữ liệu(PDF) 33 Page - National Semiconductor (TI) |
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PC87415VCG bảng dữ liệu(HTML) 33 Page - National Semiconductor (TI) |
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33 / 42 page  80 Electrical Characteristics (Continued) 842 ATAIDE Timing Specifications The following AC timing specifications are based on simulation data ATAIDE Timing Parameters Symbol Parameter Min Max Units Notes t3 CLK to DA 20 CHx CS13 DIOR 514 ns DIOW DD 150 Valid t4 DIORDY Setup Time to CLK Rising 12 ns t5 DIORDY Hold Time from CLK Rising 5 ns t6 DA 20 CHx CS13 Setup Time to DIOR 1 3 CLK 1 DIOW Falling (Data Cycles) t7 DIOR DIOW Active Time (Data Cycles) 2 16 CLK t8 DIOR DIOW Recovery Time (Data Cycles) 1 CLK t9 DD 150 Read Data Setup Time to CLK Rising 10 ns t10 DD 150 Read Data Hold Time from CLK Rising 0 ns t11 DA 20 CHx CS13 Setup Time to DIOR 1 3 CLK 1 DIOW Falling (Non Data Cycles) t12 DIOR DIOW Active Time (Non Data Cycles) 2 CLK t13 DIOR DIOW Recovery Time (Non Data Cycles) 1 CLK t14 CHx DMARQ Setup Time for the First Occurrence 7ns 2 of CHx DMARQ t15 CHx DMARQ Setup Time of the 2nd and 73 Subsequent Occurrences of CHx DMARQ t16 CLK to CHx DMACK 18 ns Note 1 Setup time is derived from the recovery field (upper 3 bits) Value of Recovery Field Setup Time in Bit 3 Bit 2 Bit 1 PCI Clocks 0 X X 4 CLKs 1 0 X 3 CLKs 1 1 0 2 CLKs 1 1 1 1 CLKs Note 2 This is an asynchronous signal The setup time is used as a reference for timing relationship of CHx DMARQ and the command generation Note 3 This is a synchronous sampling point and setup time must be met for proper operation http www nationalcom 33 |
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