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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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STA559BW bảng dữ liệu(PDF) 61 Page - STMicroelectronics |
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STA559BW bảng dữ liệu(HTML) 61 Page - STMicroelectronics |
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61 / 67 page  DocID18190 Rev 2 61/67 STA559BW Applications 67 7 Applications 7.1 Applications schematic Figure 19 below shows the typical applications schematic for STA559BW. Special attention has to be paid to the layout of the PCB. All the decoupling capacitors have to be placed as close as possible to the device to limit spikes on all the supplies. 7.2 PLL filter circuit It is recommended to use the above circuit and values for the PLL loop filter to achieve the best performance from the device in general applications. Note that the ground of this filter circuit has to be connected to the ground of the PLL without any resistive path. Concerning the component values, it must be taken into account that the greater the filter bandwidth, the less is the lock time but the higher is the PLL output jitter. 7.3 Typical output configuration Figure 18 shows the typical output configuration used for BTL stereo mode. Please contact STMicroelectronics for other recommended output configurations. Figure 18. Output configuration for stereo BTL mode (RL = 8 OUT1A 100 nF 100 nF 100 nF 100 nF 6R2 6R2 330 pF 22R OUT1B 22 µH 22 µH Left 470 nF OUT2A 100 nF 100 nF 100 nF 100 nF 6R2 6R2 330 pF 22R OUT2B 22 µH 22 µH Right 470 nF |
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