ST7LITEUS2 datasheet(68/136 Pages) STMICROELECTRONICS

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10.1.4

Low power modes

10.1.5

Interrupts

They generate an interrupt if the enable bit is set in the LTCSR register and the interrupt

mask in the CC register is reset (RIM instruction).

Figure 32.

Input capture timing diagram

Table 24.

Description of low power modes

Mode

Description

Wait

No effect on Lite timer

Active-Halt

No effect on Lite timer

Halt

Lite timer stops counting

Table 25.

Interrupt events(1)

The TBF and ICF interrupt events are connected to separate interrupt vectors (see Interrupts chapter).

Interrupt event

Event

flag

Enable

control

bit

Exit

from

Wait

Exit

from

Halt

Exit

from

Active-halt

Timebase Event

TBF

TBIE

Yes

IC Event

ICF

ICIE

Yes

0004h

13-bit COUNTER

0001h

fOSC

xxh

0002h

0003h

0005h

0006h

0007h

04h

LTIC PIN

ICF FLAG

LTICR REGISTER

CLEARED

125 ns

(@ 8 MHz fOSC)

fCPU

BY S/W

07h

READING

LTIC REGISTER

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