LQFP144 datasheet(27/112 Pages) STMICROELECTRONICS

27 / 112 page

SPC560P44Lx, SPC560P50Lx

Introduction

Doc ID 14723 Rev 9

27/112

block is an integration of several individual Nexus blocks that are selected to provide the

development support interface for this device. The NDI block interfaces to the host

processor and internal busses to provide development support as per the IEEE-ISTO 5001-

2003 Class 2+ standard. The development support provided includes access to the MCU’s

internal memory map and access to the processor’s internal registers during run time.

The Nexus Interface provides the following features:

●

Configured via the IEEE 1149.1

●

All Nexus port pins operate at VDDIO (no dedicated power supply)

●

Nexus 2+ features supported

–

Static debug

–

Watchpoint messaging

–

Ownership trace messaging

–

Program trace messaging

–

Real time read/write of any internally memory mapped resources through JTAG

pins

–

Overrun control, which selects whether to stall before Nexus overruns or keep

executing and allow overwrite of information

–

Watchpoint triggering, watchpoint triggers program tracing

●

Auxiliary Output Port

–

4 MDO (Message Data Out) pins

–

MCKO (Message Clock Out) pin

–

2 MSEO (Message Start/End Out) pins

–EVTO (Event Out) pin

●

Auxiliary Input Port

–EVTI (Event In) pin

1.5.30

Cyclic redundancy check (CRC)

The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The

CRC module features:

●

Support for CRC-16-CCITT (x25 protocol):

–

x16 + x12 + x5 + 1

●

Support for CRC-32 (Ethernet protocol):

–

x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

●

Zero wait states for each write/read operations to the CRC_CFG and CRC_INP

registers at the maximum frequency

1.5.31

IEEE 1149.1 JTAG controller

The JTAG controller (JTAGC) block provides the means to test chip functionality and

connectivity while remaining transparent to system logic when not in test mode. All data

input to and output from the JTAGC block is communicated in serial format. The JTAGC

block is compliant with the IEEE standard.

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