SPC560P50L5 datasheet(51/112 Pages) STMICROELECTRONICS

51 / 112 page

SPC560P44Lx, SPC560P50Lx

Electrical characteristics

Doc ID 14723 Rev 9

51/112

Figure 5 shows the constraints of the different power supplies.

VINAN0

ADC0 and shared ADC0/1 analog

input voltage(6)

VDD_HV_REG >

2.7 V

VSS_HV_ADV0 −

0.3

VDD_HV_ADV0 +

0.3

VDD_HV_REG <

2.7 V

VSS_HV_ADV0

VDD_HV_ADV0

VINAN1

SR ADC1 analog input voltage(7)

VDD_HV_REG >

2.7 V

VSS_HV_ADV1 −

0.3

VDD_HV_ADV1 +

0.3

VDD_HV_REG <

2.7 V

VSS_HV_ADV1

VDD_HV_ADV1

IINJPAD

Injected input current on any pin

during overload condition

—–10

IINJSUM

Absolute sum of all injected input

currents during overload condition

—–50

IVDD_LV

Low voltage static current sink

through VDD_LV

——

155

TSTG

SR Storage temperature

—

–55

150

°C

SR Junction temperature under bias

—

–40

150

°C

Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings

only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device

reliability or cause permanent damage to the device.

Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress

have not yet been determined.

The difference between each couple of voltage supplies must be less than 300 mV,

|VDD_HV_IOy – VDD_HV_IOx | < 300 mV.

The difference between ADC voltage supplies must be less than 100 mV, |VDD_HV_ADC1 – VDD_HV_ADC0| < 100 mV.

Guaranteed by device validation

Not allowed to refer this voltage to VDD_HV_ADV1, VSS_HV_ADV1

Not allowed to refer this voltage to VDD_HV_ADV0, VSS_HV_ADV0

Table 9.

Absolute maximum ratings(1) (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Max(2)

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