SPC560P50L5 datasheet(15/112 Pages) STMICROELECTRONICS

15 / 112 page

SPC560P44Lx, SPC560P50Lx

Introduction

Doc ID 14723 Rev 9

15/112

The flash memory module provides the following features:

●

As much as 576 KB flash memory

–

8 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 3×128 KB) code flash

–

4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash

–

Full Read While Write (RWW) capability between code and data flash

●

Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch

buffers can be configured to prefetch code or data or both)

●

Typical flash memory access time: 0 wait states for buffer hits, 2 wait states for page

buffer miss at 64 MHz

●

Hardware managed flash memory writes handled by 32-bit RISC Krypton engine

●

Hardware and software configurable read and write access protections on a per-master

basis

●

Configurable access timing allowing use in a wide range of system frequencies

●

Multiple-mapping support and mapping-based block access timing (up to 31 additional

cycles) allowing use for emulation of other memory types.

●

Software programmable block program/erase restriction control

●

Erase of selected block(s)

●

Read page sizes

–

Code flash memory: 128 bits (4 words)

–

Data flash memory: 32 bits (1 word)

●

ECC with single-bit correction, double-bit detection for data integrity

–

Code flash memory: 64-bit ECC

–

Data flash memory: 64-bit ECC

●

Embedded hardware program and erase algorithm

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Erase suspend, program suspend and erase-suspended program

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Censorship protection scheme to prevent flash memory content visibility

●

Hardware support for EEPROM emulation

1.5.5

Static random access memory (SRAM)

The SPC560P44Lx, SPC560P50Lx SRAM module provides up to 40 KB of general-purpose

memory.

The SRAM module provides the following features:

●

Supports read/write accesses mapped to the SRAM from any master

●

Up to 40 KB general purpose SRAM

●

Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of

memory

●

Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait state for 8-

and 16-bit writes if back to back with a read to same memory block

1.5.6

Interrupt controller (INTC)

The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt

requests, suitable for statically scheduled hard real-time systems. The INTC handles 147

selectable-priority interrupt sources.

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