SPC560P50L5 datasheet(25/112 Pages) STMICROELECTRONICS

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SPC560P44Lx, SPC560P50Lx

Introduction

Doc ID 14723 Rev 9

25/112

1.5.26

eTimer

The SPC560P44Lx, SPC560P50Lx includes two eTimer modules. Each module provides

six 16-bit general purpose up/down timer/counter units with the following features:

●

Maximum operating clock frequency of 120 MHz

●

Individual channel capability

–

Input capture trigger

–

Output compare

–

Double buffer (to capture rising edge and falling edge)

–

Separate prescaler for each counter

–

Selectable clock source

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0–100% pulse measurement

–

Rotation direction flag (Quad decoder mode)

●

Maximum count rate

–

External event counting: max. count rate = peripheral clock/2

–

Internal clock counting: max. count rate = peripheral clock

●

Counters are:

–

Cascadable

–

Preloadable

●

Programmable count modulo

●

Quadrature decode capabilities

●

Counters can share available input pins

●

Count once or repeatedly

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Pins available as GPIO when timer functionality not in use

1.5.27

Analog-to-digital converter (ADC) module

The ADC module provides the following features:

Analog part:

●

2 on-chip AD converters

–

10-bit AD resolution

–

1 sample and hold unit per ADC

–

Conversion time, including sampling time, less than 1 µs (at full precision)

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Typical sampling time is 150 ns min. (at full precision)

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Differential non-linearity error (DNL) ±1 LSB

–

Integral non-linearity error (INL) ±1.5 LSB

–TUE <3 LSB

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Single-ended input signal up to 5.0 V

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The ADC and its reference can be supplied with a voltage independent from VDDIO

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The ADC supply can be equal or higher than VDDIO

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The ADC supply and the ADC reference are not independent from each other

(they are internally bonded to the same pad)

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Sample times of 2 (default), 8, 64, or 128 ADC clock cycles

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