SPC560P50L5 datasheet(26/112 Pages) STMICROELECTRONICS

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Introduction

SPC560P44Lx, SPC560P50Lx

26/112

Doc ID 14723 Rev 9

Digital part:

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2 × 13 input channels including 4 channels shared between the 2 converters

●

4 analog watchdogs comparing ADC results against predefined levels (low, high,

range) before results are stored in the appropriate ADC result location,

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2 modes of operation: Normal mode or CTU control mode

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Normal mode features

–

ADC state machine managing 3 request flows: regular command, hardware

injected command, software injected command

–

Selectable priority between software and hardware injected commands

–

4 analog watchdogs comparing ADC results against predefined levels (low, high,

range)

–

DMA compatible interface

●

CTU control mode features

–

Triggered mode only

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4 independent result queues (2 × 16 entries, 2 × 4 entries)

–

Result alignment circuitry (left justified; right justified)

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32-bit read mode allows to have channel ID on one of the 16-bit part

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DMA compatible interfaces

1.5.28

Cross triggering unit (CTU)

The cross triggering unit allows automatic generation of ADC conversion requests on user

selected conditions without CPU load during the PWM period and with minimized CPU load

for dynamic configuration.

It implements the following features:

●

Double buffered trigger generation unit with as many as eight independent triggers

generated from external triggers

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Trigger generation unit configurable in sequential mode or in triggered mode

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Each Trigger can be appropriately delayed to compensate the delay of external low

pass filter

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Double buffered global trigger unit allowing eTimer synchronization and/or ADC

command generation

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Double buffered ADC command list pointers to minimize ADC-trigger unit update

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Double buffered ADC conversion command list with as many as 24 ADC commands

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Each trigger has the capability to generate consecutive commands

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ADC conversion command allows to control ADC channel from each ADC, single or

synchronous sampling, independent result queue selection

1.5.29

Nexus development interface (NDI)

The NDI (Nexus Development Interface) block provides real-time development support

capabilities for the SPC560P44Lx, SPC560P50Lx Power Architecture based MCU in

compliance with the IEEE-ISTO 5001-2003 standard. This development support is supplied

for MCUs without requiring external address and data pins for internal visibility. The NDI

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