SPC560B50x datasheet(83/116 Pages) STMICROELECTRONICS

83 / 116 page

DocID14619 Rev 13

83/116

SPC560B40x/50x, SPC560C40x/50x

Package pinouts and signal descriptions

115

A second aspect involving the capacitance network shall be considered. Assuming the three

capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the

equivalent circuit in Figure 19): A charge sharing phenomenon is installed when the

sampling phase is started (A/D switch close).

Figure 21. Transient behavior during sampling phase

In particular two different transient periods can be distinguished:

A first and quick charge transfer from the internal capacitance CP1 and CP2 to the

sampling capacitance CS occurs (CS is supposed initially completely discharged):

considering a worst case (since the time constant in reality would be faster) in which

CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and

CS are in series, and the time constant is

Equation 5

Equation 5 can again be simplified considering only CS as an additional worst

condition. In reality, the transient is faster, but the A/D converter circuitry has been

designed to be robust also in the very worst case: the sampling time ts is always much

longer than the internal time constant:

Equation 6

The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the

voltage VA1 on the capacitance according to Equation 7:

VA1

VA2

VCS

Voltage transient on CS

V <0.5 LSB





1 < (RSW + RAD) CS << ts



2 = RL (CS + CP1 + CP2)







---------------------











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