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SCANPSC110F bảng dữ liệu(PDF) 11 Page - National Semiconductor (TI) |
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SCANPSC110F bảng dữ liệu(HTML) 11 Page - National Semiconductor (TI) |
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11 / 29 page  Level 1 Protocol (Continued) Level 2 Protocol Once the SCANPSC110F Bridge has been successfully ad- dressed and selected, its internal registers may be accessed via Level-2 Protocol. Level-2 Protocol is compliant to IEEE Std. 1149.1 TAP protocol with one exception: if the ’PSC110F is selected via the Broadcast or Multi-Cast ad- dress, TDO B will always be TRI-STATED. (The TDOB buffer must be implemented this way to prevent bus contention.) Upon being selected, (i.e., the ’PSC110F Selection controller transitions from the Wait-For-Address state to one of the Se- lected states), each of the local scan ports (LSP 1, LSP2, LSP 3) remains parked in one of the following four TAP Con- troller states: Test-Logic-Reset, Run-Test/Idle, Pause-DR,or Pause-IR and the active scan chain will consist of: TDI B through the instruction register (or the IDCODE register) and out through TDO B. TDI B→Instruction Register→TDOB The UNPARK instruction (described later) is used to insert one or more local scan ports into the active scan chain. Table 4 describes which local ports are inserted into the chain, and in what order. LEVEL 2 INSTRUCTION TYPES There are two types of instructions (reference Table 5): DS100327-8 FIGURE 7. Broadcast Addressing: Address Loaded into Instruction Register DS100327-9 FIGURE 8. Multi-Cast Addressing: Address Loaded into Instruction Register www.national.com 11 |
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