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SCANPSC110F bảng dữ liệu(PDF) 10 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện SCANPSC110F
Giải thích chi tiết về linh kiện  SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)
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nhà sản xuất  NSC [National Semiconductor (TI)]
Trang chủ  http://www.national.com
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SCANPSC110F bảng dữ liệu(HTML) 10 Page - National Semiconductor (TI)

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Level 1 Protocol (Continued)
TABLE 4. SCANPSC110F Bridge Address Modes
Address Types
Hex Address
(Note 2)
Binary Address
(Note 3)
TDO
B State
Direct Address
00 to 3A
XX000000 to XX111010
Normal IEEE Std. 1149.1
Broadcast Address
3B
XX111011
Always TRI-STATED
Multi-Cast Group 0
3C
XX111100
Always TRI-STATED
Multi-Cast Group 1
3D
XX111101
Always TRI-STATED
Multi-Cast Group 2
3E
XX111110
Always TRI-STATED
Multi-Cast Group 3
3F
XX111111
Always TRI-STATED
Note 2: Hex address ’7X’, ’BX’, or ’FX’ may be used instead of ’3X’.
Note 3: Only the six (6) LSB’s of the address is compared to the S(0–5) inputs. The two (2) MSB’s are “don’t cares”.
DIRECT ADDRESSING
The ’PSC110F enters the
Wait-For-Address state when:
1.
its TAP Controller enters the
Test-Logic-Reset state, or
2.
its instruction register is updated with the GOTOWAIT in-
struction (while either selected or unselected).
Each ’PSC110F within a scan network must be statically
configured with a unique address via its S
(0–5) inputs. While
the ’PSC110F controller is in the
Wait-For-Address state,
data shifted into bits 5 through 0 of the instruction register is
compared with the address present on the S
(0–5) inputs in
the
Update-IR state. If the six (6) LSBs of the instruction reg-
ister match the address on the S
(0–5) inputs, (see Figure 6 )
the ’PSC110F becomes selected, and is ready to receive
Level 2 Protocol (i.e., further instructions). When the
’PSC110F is selected, its device identification register is in-
serted into the active scan chain.
All ’PSC110Fs whose S
(0–5) address does not match the in-
struction register address become unselected. They will re-
main unselected until either their TAP Controller enters the
Test-Logic-Reset state, or their instruction register is up-
dated with the
GOTOWAIT instruction.
BROADCAST ADDRESSING
The Broadcast Address allows a tester to simultaneously se-
lect all ’PSC110Fs in a test network. This mode is useful in
testing systems which contain multiple identical boards. To
avoid bus contention between scan-path output drivers on
different boards, each ’PSC110F’s TDO
B buffer is always
tri-stated while in Broadcast mode. In this configuration, the
on-chip Linear Feedback Shift Register (LFSR) can be used
to accumulate a test result signature for each board that can
be read back later by direct-addressing each board’s
’PSC110F.
MULTI-CAST ADDRESSING
As a way to make the broadcast mechanism more selective,
the ’PSC110F provides a “Multi-cast” addressing mode. A
’PSC110F’s multi-cast group register (MCGR) can be pro-
grammed to assign that ’PSC110F to one of four (4)
Multi-Cast
groups.
When
’PSC110Fs
in
the
Wait-For-Address state are updated with a Multi-Cast ad-
dress, all ’PSC110Fs whose MCGR matches the Multi-Cast
group will become selected. As in Broadcast mode, TDO
B is
always tri-stated while in Multi-cast mode.
DS100327-7
FIGURE 6. Direct Addressing: Device Address Loaded into Instruction Register
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