SCANPSC110F datasheet(1/29 Pages) NSC

tên linh kiện	SCANPSC110F

Giải thích chi tiết về linh kiện	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)

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SCANPSC110F

SCAN Bridge Hierarchical and Multidrop Addressable

JTAG Port (IEEE1149.1 System Test Support)

General Description

The SCANPSC110F Bridge extends the IEEE Std. 1149.1

test bus into a multidrop test bus environment. The advan-

tage of a hierarchical approach over a single serial scan

chain is improved test throughput and the ability to remove a

board from the system and retain test access to the remain-

ing modules. Each SCANPSC110F Bridge supports up to 3

local scan rings which can be accessed individually or com-

bined serially. Addressing is accomplished by loading the in-

struction register with a value matching that of the Slot in-

puts. Backplane and inter-board testing can easily be

accomplished by parking the local TAP Controllers in one of

the stable TAP Controller states via a Park instruction. The

32-bit TCK counter enables built in self test operations to be

performed on one port while other scan chains are simulta-

neously tested.

Features

n True IEEE1149.1 hierarchical and multidrop addressable

capability

n The 6 slot inputs support up to 59 unique addresses, a

Broadcast Address, and 4 Multi-cast Group Addresses

n 3 IEEE 1149.1-compatible configurable local scan ports

n Mode Register allows local TAPs to be bypassed,

selected for insertion into the scan chain individually, or

serially in groups of two or three

n 32-bit TCK counter

n 16-bit LFSR Signature Compactor

n Local TAPs can be tri-stated via the OE input to allow

an alternate test master to take control of the local TAPs

n The IP version of this device supports features not

described in this datasheet such as 8 slot inputs for

enhanced address capability and additional instructions.

For a completed description of the additional instructions

supported, refer to the SCANPSC110 supplemental

datasheet.

Connection Diagrams

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

28-Pin

CDIP and Flatpak

DS100327-1

Pin Assignment for LCC

DS100327-2

October 1999

DS100327

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Số phần tương tự - SCANPSC110F

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Fairchild Semiconductor	SCANPSC110F	270Kb / 25P	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)
Fairchild Semiconductor	SCANPSC110FSC	270Kb / 25P	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)

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Mô tả tương tự - SCANPSC110F

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Texas Instruments	SN54ABT8996	564Kb / 40P	10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS
Texas Instruments	SN54LVT8996	717Kb / 44P	3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS
National Semiconductor ...	SCANSTA111	524Kb / 29P	Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port
Texas Instruments	SN74LVT8986	880Kb / 47P	3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
Fairchild Semiconductor	SCANPSC110F	270Kb / 25P	SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)
National Semiconductor ...	SCANSTA111	911Kb / 31P	Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port
Texas Instruments	SN54LVT8996	603Kb / 41P	3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
	SN74LVT8986	885Kb / 54P	3.3-V LINKING ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS
	SCANSTA111	1Mb / 38P	SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port
	SN54ABT8996	741Kb / 46P	10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

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