HMC832LP6GETR datasheet(15/49 Pages) AD

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HMC832

Data Sheet

THEORY OF OPERATION

Figure 38. PLL and VCO Subsystems

The HMC832 PLL with integrated VCO is comprised of two

subsystems; PLL subsystem and VCO subsystem, as shown in

Figure 38.

PLL SUBSYSTEM OVERVIEW

The PLL subsystem divides down the VCO output to the

desired comparison frequency via the N-divider (integer value

set in Register 0x03, fractional value set in Register 0x04),

compares the divided VCO signal to the divided reference

signal (reference divider set in Register 0x02) in the phase

detector (PD), and drives the VCO tuning voltage via the charge

pump (CP) (configured in Register 0x09) to the VCO

subsystem. Some of the additional PLL subsystem functions

include

•

Delta-sigma configuration (Register 0x06).

•

Exact frequency mode (configured in Register 0x0C,

•

Lock detect (LD) configuration (use Register 0x07 to

configure LD and Register 0x0F to configure the LD_SDO

output pin).

•

External CEN pin used for the hardware PLL enable pin.

CEN pin does not affect the VCO subsystem.

Typically, only writes to the divider registers (integer part uses

subsystem are required for HMC832 output frequency changes.

Divider registers of the PLL subsystem (Register 0x03 and

3000 MHz) of the VCO subsystem. Output frequencies ranging

from 25 MHz to 1500 MHz are generated by tuning to the

appropriate fundamental VCO frequency (1500 MHz to

3000 MHz) by programming the N divider (Register 0x03 and

1/2/4/6 … /60/62, in VCO_REG 0x02) in the VCO subsystem.

For detailed frequency tuning information and example, see the

Frequency Tuning section.

VCO SUBSYSTEM OVERVIEW

The VCO subsystem consists of a capacitor switched step tuned

VCO and an output stage. In typical operation, the VCO

subsystem is programmed with the appropriate capacitor switch

setting that is executed automatically by the PLL subsystem

autocalibration state machine when autocalibration is enabled

(Register 0x0A[11] = 0, see the VCO Calibration section for

more information). The VCO tunes to the fundamental

frequency (1500 MHz to 3000 MHz), and is locked by the CP

output from the PLL subsystem. The VCO subsystem controls

the output stage of the HMC832 enabling configuration of

•

User defined performance settings (see the Programmable

Performance Technology section) that are configured via

VCO_REG 0x03[1:0].

•

VCO output divider settings that are configured in the

VCO_REG 0x02 (divide by 2/4/6 … 60/62 to generate

frequencies from 25 MHz to 1500 MHz, or divide by 1 to

generate fundamental frequencies between 1500 MHz and

3000 MHz).

•

Output gain settings (VCO_REG 0x07[3:0]).

•

Output return loss setting (VCO_REG 0x03[5]). See

Figure 26 for more information.

•

Single-ended or differential output operation

(VCO_REG 0x03[3:2]).

•

Mute (VCO_REG 0x03[8:7]).

SPI (SERIAL PORT INTERFACE) CONFIGURATION

OF PLL AND VCO SUBSYSTEMS

The two subsystems (PLL subsystem and VCO subsystem) have

their own register maps as shown in the PLL Register Map and

VCO Subsystem Register Map sections. Typically, writes to both

tuning operations.

As shown in Figure 38, the PLL subsystem is connected directly

to the SPI of the HMC832, whereas the VCO subsystem is

connected indirectly through the PLL subsystem to the

RF_N

RF_P

VTUNE

REF BUFF

RF BUFFER EN

PLL BUFF

VSPI

CAL

CONTROL

MODULATOR

CHARGE

PUMP

PHASE

FREQUENCY

DETECTOP

DIVIDER

PLL ONLY

XREFP

CEN

SEN

SDI

SCK

LD_SDO

DIVIDER

CAL

VCO EN

CNTRL

fO OR ÷N OR ×2

Rev. A | Page 14 of 48

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