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HMC832LP6GETR bảng dữ liệu(PDF) 37 Page - Analog Devices

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HMC832
Data Sheet
PLL REGISTER MAP
ID, READ ADDRESS, AND RST REGISTERS
The ID register is read only, the read address/RST strobe register is write only, and the RST register is read/write.
Table 13. Register 0x00, ID Register (Read Only)
Bits
Type
Name
Width
Default
Description
23:0
R
CHIP_ID
24
A7975
HMC832LP6GE chip ID
Table 14. Register 0x00, Read Address/RST Strobe Register (Write Only)
Bits
Type
Name
Width
Default1
Description
4:0
W
Read address
5
N/A
Read address for next cycle, open mode only. This is a write only register.
5
W
Soft reset
1
N/A
Soft reset for both SPI modes (set to 0 for proper operation).
23:6
W
Not defined
18
N/A
Not defined (set to 0 for proper operation).
1
N/A means not applicable.
Table 15. Register 0x01, RST Register (Default 0x000002)
Bits
Type
Name
Width
Default
Description
0
R/W
RST_CHIPEN_PIN_SELECT
1
0
1 = take PLL enable via CEN pin, see the Power-Down Mode section
0 = take PLL enable via SPI (RST_CHIPEN_FROM_SPI) Register 0x01[1]
1
R/W
RST_CHIPEN_FROM_SPI
1
1
PLL enable bit of the SPI
9:2
R/W
Reserved
8
0
Reserved
REFERENCE DIVIDER, INTEGER, AND FRACTIONAL FREQUENCY REGISTERS
Table 16. Register 0x02, REFDIV Register (Default 0x000001)
Bits
Type
Name
Width
Default
Description
13:0
R/W
RDIV
14
1
Reference divider R value (see Equation 12). Using the divider requires the Analog EN
Register 0x08[3] = 1 and divider, minimum = 1d, maximum = 16,383d.
Table 17. Register 0x03, Frequency Register, Integer Part (Default 0x000019)
Bits
Type
Name
Width
Default
Description
18:0
R/W
INTG_REG
19
25d
Integer divider register. These bits are the VCO divider integer part, used in
all modes, see Equation 12.
Fractional mode.
Maximum 219 − 4 = 0x7FFFC = 524,284d.
Integer mode.
Minimum 16d.
Maximum 219− 1 = 0x7FFFF = 524,287d.
Table 18. Register 0x04, Frequency Register, Fractional Part (Default 0x000000)
Bits
Type
Name
Width
Default
Description
23:0
R/W
FRAC
24
0
VCO divider fractional part (24-bit unsigned), see the Fractional Frequency Tuning section.
These bits are used in fractional mode only (NFRAC = Register 0x04/224). Minimum = 0d;
maximum = 224 − 1.
Rev. A | Page 36 of 48



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