HMC832LP6GETR datasheet(38/49 Pages) AD

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Data Sheet

HMC832

VCO SPI REGISTER

the VCO subsystem. Writes to Register 0x05 are automatically

forwarded to the VCO subsystem by the VCO SPI state

machine controller.

holds only the contents of the last transfer to the VCO subsystem.

Therefore, it is not possible to read the full contents of the VCO

subsystem. Only the content of the last transfer to the VCO

subsystem can be read. Also note special considerations for

autocalibration related to Register 0x05.

Table 19. Register 0x05, VCO SPI Register (Default 0x000000)

Bits

Type

Name

Width

Default

Description

2:0

R/W

VCO_ID

Internal VCO subsystem ID.

6:3

R/W

VCO_REGADDR

VCO subsystem register address. These bits are for

interfacing with the VCO. See the VCO Serial Port Interface

(VSPI) section.

15:7

R/W

VCO_DATA

VCO subsystem data. These bits are for the data to be

written to the VCO subsystem.

DELTA-SIGMA CONFIGURATION

Table 20. Register 0x06, Delta-Sigma Configuration Register (Default 0x200B4A)

Bit

Type

Name

Width

Default

Description

1:0

R/W

Seed

Selects the seed in fractional mode. Writes to this register are stored in

theHMC832 and are loaded into the modulator only when a frequency change is

executed and if Register 0x06[8] = 1.

00: 0 seed.

01: LSB seed.

02: 0xB29D08 seed.

03: 0x50F1CD seed.

6:2

R/W

Reserved

18d

Reserved.

R/W

FRAC_BYPASS

Bypass fractional mode. In the bypass fractional modulator, output is ignored, but

fractional modulator continues to be clocked when FRAC_RST = 1. This bit can be

used to test the isolation of the digital fractional modulator from the VCO output

in integer mode.

0: use modulator, required for fractional mode

1: bypass modulator, required for integer mode.

10:8

R/W

Initialization

Program to 7d.

R/W

SD enable

This bit controls whether autocalibration starts on an integer or a fractional write.

0: disables fractional core, use for integer mode or integer mode with CSP.

1: enables fractional core, required for fractional mode, or integer isolation

testing.

20:12

R/W

Reserved

Reserved.

R/W

Automatic clock

configuration

Program to 0.

R/W

Reserved

Reserved.

Rev. A | Page 37 of 48

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