HMC832LP6GETR datasheet(29/49 Pages) AD

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HMC832

Data Sheet

To switch between various equally spaced intervals (channels)

only the fractional register (Register 0x04) needs to be

programmed to the desired VCO channel frequency (fVCOk) in

the following manner:













−

VCOk

FRAC

ceil

)

(

where fN = floor(fVCO1/fPD), and fVCO1, as shown in Figure 46,

represents the smallest channel VCO frequency that is greater

than fN.

Example: to configure the HMC832 for the exact frequency

mode for equally spaced intervals of 100 kHz, where the first

channel (Channel 1) = fVCO1 = 2800.200 MHz and the PD rate

(fPD) = 61.44 MHz, proceed as follows:

1. Check that the exact frequency mode for this fVCO1 =

2800.2 MHz (Channel 1) and fVCO2 = 2800.2 MHz +

100 kHz = 2800.3 MHz (Channel 2) is possible.













≥













≥

)

(

)

(

GCD2

VCO2

GCD2

GCD1

VCO

GCD1

and

GCD

and

GCD

(17)

3750

120

)

2800

(

= GCD

fGCD1

3750

)

2800

(

= GCD

fGCD2

2. If Equation 16 is satisfied for at least two of the equally

spaced interval (channel) frequencies fVCO1, fVCO2, fVCO3, ...

fVCON, as it is in Equation 17, HMC832 exact frequency

channel mode is possible for all desired channel

frequencies, and can be configured as follows:

x2D

2800

























floor

VCO1

0xC00

3072

20000

)

100

(

)

((

−

GCD

VCOk

where (fVCOk+1 − fVCOk) is the desired channel spacing

(100 kHz in this example).

3. To program Register 0x04, the closest integer-N boundary

frequency, fN, that is less than the smallest channel VCO

frequency, fVCO1, must be calculated (fN = floor(fVCO1/fPD)).

Using the current example:

MHz

2764

2800













floor

Then, for Channel 1,













−

VCO1

)

(

224

where fVCO1 = 2800.2 MHz.

938000

9666560

)

2764

2800

(













−

= ceil

4. To change from Channel 1 (fVCO1 = 2800.2 MHz) to

Channel 2 (fVCO2 = 2800.3 MHz), only Register 0x04 needs

to be programmed, as long as all of the desired exact

frequencies, fVCOk (Figure 46), fall between the same

integer-N boundaries (fN < fVCOk < fN+ 1). In that case,

and

EAAB

9693867

)

2764

2800

(













−

ceil

Seed Register

The start phase of the fractional modulator digital phase

accumulator (DPA) can be set to one of four possible default

values via the seed register, Register 0x06[1:0]. The HMC832

automatically reloads the start phase (seed value) into the DPA

every time a new fractional frequency is selected. Certain zero

or binary seed values may cause spurious energy correlation at

specific frequencies. For most cases a random (not zero and not

binary) start seed is recommended (Register 0x06[1:0] = 2).

SOFT RESET AND POWER-ON RESET

The HMC832 features a hardware power-on reset (POR). All

chip registers are reset to default states approximately 250 μs

after power up.

The PLL subsystem SPI registers can also be soft reset by an SPI

write to Register 0x00. Note that the soft reset does not clear the

SPI mode of operation referred to in the Serial Port section.

Note that the VCO subsystem is not affected by the PLL soft

reset; the VCO subsystem registers can only be reset by

removing the power supply.

If external power supplies or regulators have rise times slower

than 250 μs, then it is advised to write to the SPI reset register

(Register 0x00[5] = 1) immediately after power up, before any

other SPI activity. This write procedure ensures starting from a

known state.

Rev. A | Page 28 of 48

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