MB95650L datasheet(67/105 Pages) CYPRESS

67 / 105 page

Document Number: 002-04696 Rev. *A

Page 67 of 105

MB95650L Series

(Continued)

(VCC = 1.8 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)

*1: This is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits

(SYCC:DIV[1:0]). This source clock is divided to become a machine clock according to the division ratio set by the machine clock

division ratio select bits (SYCC:DIV[1:0]). In addition, a source clock can be selected from the following.

• Main clock divided by 2

• PLL multiplication of main clock (Select a multiplication rate from 2, 2.5, 3 and 4.)

• Main CR clock

• PLL multiplication of main CR clock (Select a multiplication rate from 2, 2.5, 3 and 4.)

• Subclock divided by 2

• Sub-CR clock divided by 2

*2: This is the operating clock of the microcontroller. A machine clock can be selected from the following.

• Source clock (no division)

• Source clock divided by 4

• Source clock divided by 8

• Source clock divided by 16

Parameter

Symbol

name

Value

Unit

Remarks

Min

Typ

Max

Machine clock

frequency

FMP

—

0.031

—

16.25

MHz When the main oscillation clock is used

0.25

—

MHz When the main CR clock is used

0.25

—

MHz When the main PLL clock is used

0.25

—

MHz When the main CR PLL clock is used

FMPL

1.024

—

16.384

kHz When the suboscillation clock is used

3.125

—

kHz

When the sub-CR clock is used

FCRL = 100 kHz

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