MPC823 datasheet(7/74 Pages) MOTOROLA

7 / 74 page

Communication Processor Module

MOTOROLA

MPC823 REFERENCE MANUAL

16-385

01 =

PowerPC little-endian byte ordering. As data is transmitted onto the serial line

from the data buffer, the least-significant byte of the buffer double-word

contains data to be transmitted earlier than the most-significant byte of the

same buffer double-word.

1X = Motorola byte ordering (normal operation) is also called big-endian byte

ordering. As data is transmitted onto the serial line from the data buffer, the

most-significant byte of the buffer word contains data to be transmitted earlier

than the least-significant byte of the same buffer word.

AT—Address Type 1–3

These bits contain the function code value used during the SDMA channel memory

access. The AT0 pin is driven with a 1 to identify this SDMA channel access as a DMA

type.

Bits 0–2—Reserved

These bits are reserved and must be set to 0.

BO—Byte Ordering

Set these bits to select the required byte ordering of the data buffer. If this field is

modified on-the-fly, it takes effect at the beginning of the next frame or the next buffer

descriptor.

00 =

The DEC/Intel convention is used for byte ordering (swapped operation) and

is also called little-endian byte ordering. The transmission order of bytes within

a buffer word is reversed in comparison to the Motorola mode. This mode is

supported only for 32-bit port size memory.

01 =

PowerPC little-endian byte ordering. As data is transmitted onto the serial line

from the data buffer, the least-significant byte of the buffer double-word

contains data to be transmitted earlier than the most-significant byte of the

same buffer double-word.

1X = Motorola byte ordering (normal operation) is also called big-endian byte

ordering. As data is transmitted onto the serial line from the data buffer, the

most-significant byte of the buffer word contains data to be transmitted earlier

than the least-significant byte of the same buffer word.

TFCR

BIT

FIELD

RESERVED

AT1–AT3

RESET

000

R/W

ADDR

SMC1 AND SMC2 BASE + 0x05

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