MYX29GL01GS11DPIV2 datasheet(2/68 Pages) MICROSS

2 / 68 page

MYX29GL01GS11DPIV2

Revision 1.0 - 01/26/2015

*Advanced information. Subject to change without notice.

1Gb GL-S MirrorBit® Eclipse™

Flash Memory

MYX29GL01GS11DPIV2*

Form #: CSI-D-685 Document 001

Contents

Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Address Space Maps . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1

Flash Memory Array........................... 7

2.2

Device ID and CFI (ID-CFI) ASO ................... 7

2.3

Status Register ASO........................... 8

2.4

Data Polling Status ASO ........................ 8

2.5

Secure Silicon Region ASO ...................... 9

2.6

Sector Protection Control ....................... 9

Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.1

Device Protection Methods ..................... 10

3.2

Command Protection ......................... 11

3.3

Secure Silicon Region (OTP) .................... 12

3.4

Sector Protection Methods ..................... 12

Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.1

Asynchronous Read .......................... 17

4.2

Page Mode Read ............................ 17

Embedded Operations . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.1

Embedded Algorithm Controller (EAC) ............. 18

5.2

Program and Erase Summary ................... 19

5.3

Command Set .............................. 20

5.4

Status Monitoring ........................... 25

5.5

Error Types and Clearing Procedures.............. 26

5.6

Embedded Algorithm Performance Table ........... 27

Software Interface Reference . . . . . . . . . . . . . . . . . . . .28

6.1

Command Summary ......................... 28

6.2

Device ID and Common Flash

Interface (ID-CFI) ASO Map..................... 32

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

7.1

AddressandDataConfiguration . . . . . . . . . . . . . . . . . 38

7.2

Input/Output Summary........................ 38

7.3

Versatile I/O Feature.......................... 39

7.4

Ready/Busy# (RY/BY#) ........................ 39

7.5

Hardware Reset............................. 40

Signal Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

8.1

Interface States ............................. 40

8.2

Power-Off with Hardware Data Protection .......... 42

8.3

Power Conservation Modes .................... 42

8.4

Read..................................... 43

ElectricalSpecifications. . . . . . . . . . . . . . . . . . . . . . . .45

9.1

Absolute Maximum Ratings .................... 45

9.2

Latchup Characteristics ....................... 45

9.3

Operating Ranges ........................... 46

9.4

DC Characteristics ........................... 48

9.5

Capacitance Characteristics .................... 50

TimingSpecifications. . . . . . . . . . . . . . . . . . . . . . . . . .50

10.1

AC Test Conditions........................... 50

10.2

Power-On Reset (POR) and Warm Reset ........... 51

10.3

AC Characteristics ........................... 54

Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

11.1

Connection Diagram ......................... 63

11.2

Physical Diagram – LAE064 .................... 64

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .65

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