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MYX29GL01GS11DPIV2 bảng dữ liệu(PDF) 47 Page - Micross Components |
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MYX29GL01GS11DPIV2 bảng dữ liệu(HTML) 47 Page - Micross Components |
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47 / 68 page  MYX29GL01GS11DPIV2 Revision 1.0 - 01/26/2015 *Advanced information. Subject to change without notice. 47 1Gb GL-S MirrorBit® Eclipse™ Flash Memory MYX29GL01GS11DPIV2* Form #: CSI-D-685 Document 001 Table 17: Power-Up/Power-Down Voltage and Timing Symbol Parameter Min Max Unit VCC VCC Power Supply 2.7 3.6 V VLKO VCC level below which re-initialization is required1 2.25 2.5 V VRST VCC and VIO Low voltage needed to ensure initialization will occur1 1.0 V tVCS VCC and VIO ≥minimumtofirstaccess1 300 μs tPD Duration of VCC ≤ VRST(min)1 15 μs Note:1.Not100%tested. Figure 3: Power-up 72 GL-S MirrorBit® Family S29GL_128S_01GS_00_08 October 9, 2013 D a t a S h e e t Note: 1. Not 100% tested. Figure 9.1 Power-up Figure 9.2 Power-down and Voltage Drop Table 9.2 Power-Up/Power-Down Voltage and Timing Symbol Parameter Min Max Unit VCC VCC Power Supply 2.7 3.6 V VLKO VCC level below which re-initialization is required (Note 1) 2.25 2.5 V VRST VCC and VIO Low voltage needed to ensure initialization will occur (Note 1) 1.0 V tVCS VCC and VIO ≥ minimum to first access (Note 1) 300 µs tPD Duration of VCC ≤ VRST(min) (Note 1) 15 µs Vcc (m ax) Vcc (m in) Power Supply Voltage tim e tVCS Full Device Access Vcc VIO (m in) VIO (m ax) VIO VCC (m ax) VCC (m in) VCC and VIO tim e VRST (m in) tPD tVCS No Device Access Allowed Full Device Access Allowed VLKO (m ax) Figure 4: Power-down and Voltage Drop 72 GL-S MirrorBit® Family S29GL_128S_01GS_00_08 October 9, 2013 D a t a S h e e t Note: 1. Not 100% tested. Figure 9.1 Power-up Figure 9.2 Power-down and Voltage Drop Table 9.2 Power-Up/Power-Down Voltage and Timing Symbol Parameter Min Max Unit VCC VCC Power Supply 2.7 3.6 V VLKO VCC level below which re-initialization is required (Note 1) 2.25 2.5 V VRST VCC and VIO Low voltage needed to ensure initialization will occur (Note 1) 1.0 V tVCS VCC and VIO ≥ minimum to first access (Note 1) 300 µs tPD Duration of VCC ≤ VRST(min) (Note 1) 15 µs Vcc (m ax) Vcc (m in) Power Supply Voltage tim e tVCS Full Device Access Vcc VIO (m in) VIO (m ax) VIO VCC (m ax) VCC (m in) VCC and VIO tim e VRST (m in) tPD tVCS No Device Access Allowed Full Device Access Allowed VLKO (m ax) |
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