MYX29GL01GS11DPIV2 datasheet(44/68 Pages) MICROSS

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MYX29GL01GS11DPIV2

Revision 1.0 - 01/26/2015

*Advanced information. Subject to change without notice.

1Gb GL-S MirrorBit® Eclipse™

Flash Memory

MYX29GL01GS11DPIV2*

Form #: CSI-D-685 Document 001

8.4.4

Asynchronous Write

WhenWE#goesLowafterCEisLow,thereisatransitionfromoneofthereadstatestotheWritestate.IfWE#

isLowbeforeCE#goesLow,thereisatransitionfromtheStandbystatedirectlytotheWritestatewithout

beginningareadaccess.

WhenCE#isLow,OE#isHigh,andWE#goesLow,awritedatatransferbegins.Note,OE#andWE#should

neverbeLowatthesametimetoensurenodatabuscontentionbetweenthehostsystemandmemory.When

theasynchronouswritecycletimingrequirementsaremettheWE#cangoHightocapturetheaddressand

datavaluesintoEACcommandmemory.

AddressiscapturedbythefallingedgeofWE#orCE#,whicheveroccurslater.Dataiscapturedbytherising

edgeofWE#orCE#,whicheveroccursearlier.

WhenCE#isLowbeforeWE#goesLowandstaysLowafterWE#goesHigh,theaccessiscalledaWE#

controlledWrite.WhenWE#isHighandCE#goesHigh,thereisatransitiontotheStandbystate.IfCE#

remainsLowandWE#goesHigh,thereisatransitiontotheReadwithOutputDisablestate.

WhenWE#isLowbeforeCE#goesLowandremainsLowafterCE#goesHigh,theaccessiscalledaCE#

controlledWrite.ACE#controlledWritetransitionstotheStandbystate.

IfWE#isLowbeforeCE#goesLow,thewritetransferisstartedbyCE#goingLow.IfWE#isLowafterCE#

goesHigh,theaddressanddataarecapturedbytherisingedgeofCE#.ThesecasesarereferredtoasCE#

controlledwritestatetransitions.

WritefollowedbyReadaccesses,inwhichCE#remainsLowbetweenaccesses,requiresanaddresschange

toinitiatethefollowingreadaccess.

BacktoBackaccesses,inwhichCE#remainsLowbetweenaccesses,requiresanaddresschangetoinitiate

thesecondaccess.

TheEACcommandmemoryarrayisnotreadablebythehostsystemandhasnoASO.TheEACexaminesthe

addressanddataineachwritetransfertodetermineifthewriteispartofalegalcommandsequence.Whena

legalcommandsequenceiscompletetheEACwillinitiatetheappropriateEA.

8.4.5

Write Pulse “Glitch” Protection

Noisepulsesoflessthan5ns(typical)onWE#willnotinitiateawritecycle.

8.4.6

Logical Inhibit

WritecyclesareinhibitedbyholdingOE#atVIL,orCE#atVIH,orWE#atVIH.Toinitiateawritecycle,CE#and

WE#mustbeLow(VIL)whileOE#isHigh(VIH).

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