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MT9072AB bảng dữ liệu(PDF) 259 Page - Zarlink Semiconductor Inc

tên linh kiện MT9072AB
Giải thích chi tiết về linh kiện  Octal T1/E1/J1 Framer
PDF  275 Pages
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nhà sản xuất  ZARLINK [Zarlink Semiconductor Inc]
Trang chủ  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB bảng dữ liệu(HTML) 259 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
259
Zarlink Semiconductor Inc.
19.2.1
AC Electrical Characteristics - PCM24 and ST-BUS Frame Format
In both the transmit and receive directions, PCM24 LSB maps to ST-BUS LSB.
Figure 55 - PCM 24 Format
Figure 56 - ST-BUS Format
‡Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Note 1. High impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge
CL.
FRAME
15
0
14
15
0
timeslot
01
30
31
Most
Significant
Bit (First)
Least
Significant
Bit (Last)
BIT
12
3
4
56
7
8
FRAME
FRAME
FRAME
FRAME
timeslot
timeslot
timeslot
BIT
BIT
BIT
BIT
BIT
BIT
BIT
2.0 ms
(8/2.048)
µs
125
µs
•• •• •• ••
•• ••
CHANNEL
31 or 127
0
30 or 126
BIT
CHANNEL
CHANNEL
CHANNEL
CHANNEL
31 or 127
0
BIT
BIT
BIT
BIT
BIT
BIT
BIT
• • •
Least
Significant
Bit (Last)
Most
Significant
Bit (First)
125
µs
76
5
4
3
2
1
0
(8/2.048 or 8/8.192)
µs



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