MT9072AB datasheet(128/275 Pages) ZARLINK

128 / 275 page

MT9072

Data Sheet

128

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

15-14

not used.

13-11

PI2-0

Phase Indicator Bits (PI2 to PI0). These bits make up 3 least significant bits of a 12 bit

word which indicate the delay through the receive slip buffer. The delay through the slip

buffer in 2.048 Mhz bit cells is ( 512 - Phase Indicator bits). The delay to DSTo from the

write into the slip buffer is ( 512 - Phase Indicator bits) + 16 bits. These bits are updated

when the slip buffer write address is 0. These 3 bits will reflect the 1/2,1/4 and 1/8

fractions of the Phase Indicator Bits.

RSLPD

Receive Slip Direction. If one, indicates that the last received frame slip resulted in a

repeated frame, i.e., the system clock (C4b) is faster than network clock (EXCLi). If zero,

indicates that the last received frame slip resulted in a lost frame, i.e., system clock slower

than network clock. Updated on an RSLIP occurrence basis.

9RxSLIP

Receive Slip. A change of state (i.e., 1-to-0 one 0-to-1) indicates that a receive controlled

frame slip has occured.

8RxFRM

Receive Frame. The most significant bit of the phase status word. If one, the delay

through the receive elastic buffer is greater than one frame in length; if zero, the delay

through the receive elastic buffer is less than one frame in length.

7-3

RxTS4 - 0 Receive Timeslot. A five bit counter that indicates the number of timeslots between the

receive elastic buffer internal write frame boundary and the ST-BUS read frame boundary.

The count is updated every 250 uS.

2-0

RxBC2 - 0 Receive Bit Count. A three bit counter that indicates the number of ST-BUS bit times

there are between the receive elastic buffer internal write frame boundary and the ST-BUS

read frame boundary. The count is updated every 250 uS.

Table 82 - Receive Slip Buffer Status Word(Y13) (T1)

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