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ST92185B bảng dữ liệu(PDF) 61 Page - STMicroelectronics

tên linh kiện ST92185B
Giải thích chi tiết về linh kiện  16K/24K/32K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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ST92185B - RESET AND CLOCK CONTROL UNIT (RCCU)
4.5 RESET CONTROL UNIT REGISTERS
The RCCU consists of two registers. They are
PCONF and SDRATH. Unless otherwise stated,
unused register bits must be kept in their reset val-
ue in order to avoid problems with the device be-
haviour.
PLL CONFIGURATION REGISTER (PCONF)
R251 - Read/Write
Register Page: 55
Reset value: 0000 0111 (07h)
Bit 7= SRESEN.
Software Reset Enable.
0: RCCU PLL and CSDU are turned off when a
HALT instruction is performed.
1: RCCU will reset the microcontroller when a
HALT instruction is performed.
Bit 6:0= Reserved bits. Leave in their reset state.
CLOCK SLOW DOWN UNIT RATIO REGISTER
(SDRATH)
R254 - Read/Write
Register Page: 55
Reset value:
0010 0xxx (2xh) after software reset
0100 0xxx (4xh) after watchdog reset
0000 0000 (00h) after external reset
Bit 7 = Reserved bit. Leave in its reset state.
Bit 6 = WDGRES.
Watchdog Reset. WDGRES is
automatically set if the last reset was a watchdog
Reset. This is a read only bit.
Bit 5 = SFTRES.
Software Reset. SFTRES is au-
tomatically set if the last reset was a software Re-
set. This is a read only bit.
Bit 4:0 = Reserved bits. Please leave in their reset
state.
70
SRESEN
0
0
0
0
1
1
1
70
0
WDGRES SFTRES
0
0
x
x
x



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