ST92185B datasheet(65/178 Pages) STMICROELECTRONICS

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ST92185B - TIMING AND CLOCK CONTROLLER

5.2 REGISTER DESCRIPTION

MAIN CLOCK CONTROL REGISTER (MCCR)

R253 - Read/ Write

Reset value: 0000 0000 (00h)

The HALT mode forces the register to its initializa-

tion state.

Bit 7 = FMEN.

Frequency Multiplier Enable bit.

0: FM disabled (reset state), low-power consump-

tion mode.

1: FM is enabled, providing clock to the CPU. The

FMEN bit must be set only after programming

the FML(3:0) bits.

Bit 6= FMSL.

Frequency Multiplier Select bit.

This bit controls the choice of the ST9+ core inter-

nal frequency between the external crystal fre-

quency and the Main Clock issued by the frequen-

cy multiplier.

In order to secure the application, the ST9+ core

internal frequency is automatically switched back

to the external crystal frequency if the frequency

multiplier is switched off (FMEN =0) regardless of

the value of the FMSL bit. Care must be taken to

reset the FMSL bit before any frequency multiplier

can restart (FMEN set back to 1).

After reset, the external crystal frequency is al-

ways sent to the ST9+ Core.

Bit 5:4 = These bits are reserved.

Bit 3:0 = FML[3:0]

Frequency bits.

These 4 bits program the down-counter inserted in

the feed-back loop of the Frequency Multiplier

which generates the internal multiplied frequency

Fimf. The Fimf value is calculated as follows :

Fimf = Crystal frequency * [ (FML(3:0) + 1) ] /2

SKEW CLOCK CONTROL REGISTER (SKCCR)

R254 - Read/ Write

Reset value: 0000 0000 (00h)

The HALT mode forces the register to its initializa-

tion state.

Bit 7= SKWEN.

Frequency Multiplier Enable bit.

0: FM disabled (reset state), low-power consump-

tion mode.

1: FM is enabled, supplying the clock to the Skew

corrector. The SKWEN bit must be set only after

programming the SKW(3-0) bits.

Bit 6= SKDIV2.

Divide-by-2 enable

This bit determines whether a divide-by-2 down-

scaling factor is applied to the output of the Skew

Corrector.

0 = Divide-by-2 enabled

1 = Divide-by-2 disabled

Bit 5:4 = These bits are reserved.

Bit 3:0 = SKW[3:0].

Frequency bits

These 4 bits program the down-counter inserted in

the feedback loop of the Frequency Multiplier

which generates the internal multiplied frequency

DOTCK. The DOTCK value is calculated as fol-

lows :

F(DOTCK) = Crystal frequency * [ (SKW(3:0) + 1) ]

321

FMEN FMSL

FML3 FML2 FML1 FML0

SKW

SKDIV2

SKW3 SKW2 SKW1 SKW0

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