ST92185B datasheet(77/178 Pages) STMICROELECTRONICS

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ST92185B - TIMER/WATCHDOG (WDT)

TIMER/WATCHDOG (Cont’d)

7.1.4 WDT Interrupts

The Timer/Watchdog issues an interrupt request

at every End of Count, when this feature is ena-

bled.

A pair of control bits, IA0S (EIVR.1, Interrupt A0 se-

lection bit) and TLIS (EIVR.2, Top Level Input Se-

lection bit) allow the selection of 2 interrupt sources

(Timer/Watchdog End of Count, or External Pin)

handled in two different ways, as a Top Level Non

Maskable Interrupt (Software Reset), or as a

source for channel A0 of the external interrupt logic.

A block diagram of the interrupt logic is given in

Figure 3.

Note: Software traps can be generated by setting

the appropriate interrupt pending bit.

Table 1 below, shows all the possible configura-

tions of interrupt/reset sources which relate to the

Timer/Watchdog.

A reset caused by the watchdog will set bit 6,

WDGRES of R242 - Page 55 (Clock Flag Regis-

ter). See section CLOCK CONTROL REGIS-

TERS.

Figure 46. Interrupt Sources

Table 14. Interrupt Configuration

Legend:

WDG = Watchdog function

SW TRAP = Software Trap

Note: If IA0S and TLIS = 0 (enabling the Watchdog EOC as interrupt source for both Top Level and INTA0

interrupts), only the INTA0 interrupt is taken into account.

TIMER WATCHDOG

RESET

WDGEN (WCR.6)

INTA0 REQUEST

IA0S (EIVR.1)

MUX

INT0

MUX

TOP LEVEL

INTERRUPT REQUEST

VA00293

TLIS (EIVR.2)

NMI

Control Bits

Enabled Sources

Operating Mode

WDGEN

IA0S

TLIS

Reset

INTA0

Top Level

WDG/Ext Reset

SW TRAP

Ext Pin

SW TRAP

Ext Pin

SW TRAP

Ext Pin

Watchdog

Ext Reset

Timer

Ext Pin

Timer

Ext Pin

Timer

Ext Pin

Timer

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