ST92185B datasheet(145/178 Pages) STMICROELECTRONICS

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ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)

SERIAL PERIPHERAL INTERFACE (Cont’d)

7.6.5 Working With Other Protocols

The SPI peripheral offers the following facilities for

operation with S-bus/I2C-bus and IM-bus proto-

cols:

Interrupt request on start/stop detection

Hardware clock synchronisation

Arbitration lost flag with an automatic set of data

line

Note that the I/O bit associated with the SPI should

be returned to a defined state as a normal I/O pin

before changing the SPI protocol.

The following paragraphs provide information on

how to manage these protocols.

7.6.6 I2C-bus Interface

The I2C-bus is a two-wire bidirectional data-bus,

the two lines being SDA (Serial DAta) and SCL

(Serial CLock). Both are open drain lines, to allow

arbitration. As shown in Figure 5, data is toggled

with clock low. An I²C bus start condition is the

transition on SDI from 1 to 0 with the SCK held

high. In a stop condition, the SCK is also high and

the transition on SDI is from 0 to 1. During both of

these conditions, if SPEN = 0 and BMS = 1 then

an interrupt request is performed.

Each transmission consists of nine clock pulses

(SCL line). The first 8 pulses transmit the byte

(MSB first), the ninth pulse is used by the receiver

to acknowledge.

Figure 89. S-Bus / I2C-bus Peripheral

Compatibility without S-Bus Chip Select

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