ST92185B datasheet(116/178 Pages) STMICROELECTRONICS

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ST92185B - ON SCREEN DISPLAY (OSD)

ON SCREEN DISPLAY (Cont’d)

7.4.6.6 Building a Serial Mode, 80 Char, Line

Mode Display

Half-Page Location:

The pair of 0.5 Kbyte blocks of half page content is

stored in the TDSRAM location pointed to by the

PG3..PG0 bits. The first block contains the left half

rows, the other block contains the right half rows.

Header/Status Rows Location:

The 0.5 Kbyte block containing the Header, Status

Row 0 and Status Row 1 is pointed to by the

HS3..HS0 bits.

The Row attribute (row count) is stored in this

block at offset 100h and contains 12 bytes for line

mode (see DCM1R register description).

Row Scrolling Buffer Location:

The scrolling buffer corresponds to Row 12 when

the scrolling feature is used (in this case 11 rows

are scrolled).

Figure 76. Serial (80 Characters) Line Mode Mapping

Figure 77. Serial (80 Characters) Line Mode - Header and Status Mapping

0.5K TDSRAM

Resolution 1K bytes

Block

Number(1K)

TDSRAM

Address Left

(hex)

TDSRAM

Address Right

(hex)

TDPR

Value (hex)

PG3..PG0

8000

8200

8400

8600

28800

8A00

8C00

8E00

9000

9200

9400

9600

69800

9A00

9C00

9E00

Row 1 Left

Row 11

Free Space

Row 12/Scroll Buffer

0.5K TDSRAM

Row 1 Right

Row 11

Free Space

Row 12/Scroll Buffer

See Figure 22 for Address Values

0.5K TDSRAM

Header

Resolution 0.5K bytes

Status Row 0

Status Row 1

Free Space

Row Attr.

100h

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