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BQ76PL455APFCT bảng dữ liệu(PDF) 68 Page - Texas Instruments |
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BQ76PL455APFCT bảng dữ liệu(HTML) 68 Page - Texas Instruments |
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68 / 125 page  68 bq76PL455A SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: bq76PL455A Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Table 8. Registers in Alphabetical Order (continued) NAME DESCRIPTION ADDR HEX ADDR DECIMAL MAGIC2 "Magic" value enables EEPROM write FC–FF 252–255 MASK_COMM Communications FAULT mask register 68–69 104–105 MASK_DEV Chip FAULT mask register 6B–6C 107–108 MASK_SYS System FAULT mask register 6A 106 NCHAN Number of channels enabled for conversion 0D 13 OVERSMPL Command averaging (oversampling) 07 7 PWRCONFIG Power configuration 0F 15 RESERVED Reserved for future use 08-09 9-Aug RESERVED Reserved for future use 16–1D 22–29 RESERVED Reserved for future use 26–27 38–39 RESERVED Reserved for future use 2C–31 44–49 RESERVED Reserved for future use 32 50 RESERVED Reserved for future use 33–36 51–54 RESERVED Reserved for future use 37 55 RESERVED Reserved for future use 38–3C 56–60 RESERVED Reserved for future use 45–4F 69–79 RESERVED Reserved for future use 64–67 100–103 RESERVED Reserved for future use 6D 109 RESERVED Reserved for future use 70–77 112–119 RESERVED Reserved for future use 7.00E–81 126–129 RESERVED Reserved for future use 86–8B 134–139 RESERVED Reserved for future use B2–BD 178–189 RESERVED Reserved for future use D0–D1 208–209 RESERVED Reserved for future use E4-E5 228–229 RESERVED Reserved for future use EE-EF 238–239 RESERVED Reserved for future use FB 251 SCRATCH User-defined data C8–CF 200–207 SER_NUM Device serial number C6–C7 198–199 SHDN_STS Shutdown recovery status 50 80 SMPL_DLY1 Initial sampling delay 3D 61 SREV Silicon Revision 00–01 0–1 STATUS Device status 51 81 TEST_ADC ADC BIST control 22–24 34–36 TEST_CSUM Checksum Test Result F8–F9 248–249 TEST_SPER ADC test sampling period 43–44 67–68 TESTAUXPU Test control—AUX pull-up resistors 25 37 TESTCTRL BIST control 20–21 32–33 TSTCONFIG Built-In Self-Test (BIST) configuration 1E–1F 30–31 TSTR_ECC ECC Test Results E6-ED 230–237 TXHOLDOFF UART Transmitter holdoff 12 18 VSGAIN ADC voltage gain correction D3 211 VSOFFSET ADC voltage offset correction D2 210 |
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