ADV7181BBCPZ datasheet(29/96 Pages) AD

29 / 96 page

ADV7181B

Rev. 0 | Page 29 of 96

CSFM[2:0] C Shaping Filter Mode, Address 0x17 [7]

The C shaping filter mode bits allow the user to select from a

range of low-pass filters for the chrominance signal. When

switched in automatic mode, the widest filter is selected based

on the video standard/format and user choice (see settings 000

and 001 in Table 30).

Table 30. CSFM Function

CSFM[2:0]

Description

000 (default)

Autoselect 1.5 MHz bandwidth

001

Autoselect 2.17 MHz bandwidth

010

SH1

011

SH2

100

SH3

101

SH4

110

SH5

111

Wideband mode

–10

–20

–30

–40

–50

–60

FREQUENCY (MHz)

v740a COMBINED C ANTIALIAS, C SHAPING FILTER,

C RESAMPLER

Figure 15. Chroma Shaping Filter Responses

Figure 15 shows the responses of SH1 (narrowest) to SH5

(widest) in addition to the wideband mode (in red).

GAIN OPERATION

The gain control within the ADV7181B is done on a purely

digital basis. The input ADCs support a 9-bit range, mapped

into a 1.6 V analog voltage range. Gain correction takes place

after the digitization in the form of a digital multiplier.

Advantages of this architecture over the commonly used PGA

(programmable gain amplifier) before the ADC include the fact

that the gain is now completely independent of supply,

temperature, and process variations.

As shown in Figure 16, the ADV7181B can decode a video

signal as long as it fits into the ADC window. The components

to this are the amplitude of the input signal and the dc level it

resides on. The dc level is set by the clamping circuitry (see the

Clamp Operation section).

If the amplitude of the analog video signal is too high, clipping

may occur, resulting in visual artifacts. The analog input range

of the ADC, together with the clamp level, determines the

maximum supported amplitude of the video signal.

The minimum supported amplitude of the input video is

determined by the ADV7181B’s ability to retrieve horizontal

and vertical timing and to lock to the color burst, if present.

There are separate gain control units for luma and chroma data.

Both can operate independently of each other. The chroma unit,

however, can also take its gain value from the luma path.

The possible AGC modes are summarized in Table 31.

It is possible to freeze the automatic gain control loops. This

causes the loops to stop updating and the AGC determined gain

at the time of the freeze to stay active until the loop is either

unfrozen or the gain mode of operation is changed.

The currently active gain from any of the modes can be read

back. Refer to the description of the dual-function manual gain

registers, LG[11:0] Luma Gain and CG[11:0] Chroma Gain, in

the Luma Gain and the Chroma Gain sections.

ANALOG VOLTAGE

RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7181B)

DATA

PRE-

PROCESSOR

(DPP)

ADC

SDP

(GAIN SELECTION ONLY)

MAXIMUM

VOLTAGE

MINIMUM

VOLTAGE

CLAMP

LEVEL

GAIN

CONTROL

Figure 16. Gain Control Overview

ADV7181BBCPZ bảng dữ liệu(PDF) 29 Page - Analog Devices

ADV7181BBCPZ bảng dữ liệu(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

bảng dữ liệu tải về

Link URL