ADV7181BBCPZ datasheet(10/96 Pages) AD

10 / 96 page

ADV7181B

Rev. 0 | Page 10 of 96

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DGND

DVDDIO

P11

P10

SFL

DGND 10

DVDDIO 11

NC 12

NC 13

P7 14

P6 15

P5 16

AIN5

AIN4

AIN3

AGND

CAPC2

AGND

CML

REFOUT

AVDD

CAPY2

CAPY1

AGND

AIN2

AIN1

DGND

ADV7181B

TOP VIEW

(Not to Scale)

NC = NO CONNECT

PIN 1

INDICATOR

INTRQ

Figure 4. 64-Lead LFCSP/LQFP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Type

Function

3, 10, 24, 34, 57

DGND

Digital Ground.

32, 37, 43, 45

AGND

Analog Ground.

4, 11

DVDDIO

Digital I/O Supply Voltage (3.3 V).

23, 58

DVDD

Digital Core Supply Voltage (1.8 V).

AVDD

Analog Supply Voltage (3.3 V).

PVDD

PLL Supply Voltage (1.8 V).

35, 36, 46–49

AIN1–AIN6

Analog Video Input Channels.

12, 13, 27, 28, 33,

50, 55, 56

No Connect Pins.

26, 25, 19, 18, 17,

16, 15, 14, 8, 7, 6, 5,

62, 61, 60, 59

P0–P15

Video Pixel Output Port.

Horizontal Synchronization Output Signal.

Vertical Synchronization Output Signal.

FIELD

Field Synchronization Output Signal.

INTRQ

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input

video. See the interrupt register map in Table 82.

SDA

I/O

I2C Port Serial Data Input/Output Pin.

SCLK

I2C Port Serial Clock Input (Maximum Clock Rate of 400 kHz).

ALSB

This pin selects the I2C address for the ADV7181B. ALSB set to a Logic 0 sets the address for

a write as 0x40; for ALSB set to a logic high, the address selected is 0x42.

RESET

System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to

reset the ADV7181B circuitry.

LLC

This is a line-locked output clock for the pixel data output by the ADV7181B. Nominally

27 MHz, but varies up or down according to video line length.

XTAL

This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V,

27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

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