PC87365 datasheet(156/215 Pages) NSC

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9.0 Voltage Level Monitor (VLM) (Continued)

156

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9.5

VLM REGISTERS

The register maps in this chapter use the following abbreviations for Type:

• R/W = Read/Write.

• R = Read from a speciﬁc address returns the value of a speciﬁc register. Write to the same address is to a different

• W = Write.

• RO = Read Only.

• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

9.5.1

VLM Register Map

Table 48. VLM Control and Status Register Map

Table 49. VLM Channel Register Map (One per Channel)

Offset

Mnemonic

Type

Section

00h

VEVSTS0

Voltage Event Status 0

9.5.2

01h

VEVSTS1

Voltage Event Status 1

9.5.3

02h

VEVSMI0

Voltage Event to SMI 0

R/W

9.5.4

03h

VEVSMI1

Voltage Event to SMI 1

R/W

9.5.5

04h

VEVIRQ0

Voltage Event to IRQ 0

R/W

9.5.6

05h

VEVIRQ1

Voltage Event to IRQ 1

R/W

9.5.7

06h

VID

Voltage ID

Varies per bit

9.5.8

07h

VCNVR

Voltage Conversion Rate

R/W

9.5.9

08h

VLMCFG

VLM Conﬁguration

R/W

9.5.10

09h

VLMBS

VLM Bank Select

R/W

9.5.11

Offset

Mnemonic

Type

Section

0Ah

VCHCFST

Voltage Channel Configuration and Status

Varies per bit

9.5.12

0Bh

RDCHV

Read Channel Voltage

9.5.13

0Ch

CHVH

Channel Voltage High Limit

R/W

9.5.14

0Dh

CHVL

Channel Voltage Low Limit

R/W

9.5.15

0Eh-

0Fh

Reserved

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