PC87365 datasheet(11/215 Pages) NSC

11 / 215 page

Table of Contents (Continued)

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10.2.2

TOS, THIGH and TLOW Limits, OTS and ALERT Output, IRQ and SMI ...................... 170

10.2.3

ALERT Response Read Sequence ........................................................................... 171

10.2.4

Power-On Reset Default States ................................................................................ 171

10.2.5

Temperature Data Format ......................................................................................... 172

10.2.6

Standby Mode ........................................................................................................... 172

10.2.7

Diode Fault Detection ................................................................................................ 172

10.3

TMS REGISTERS ................................................................................................................... 173

10.3.1

TMS Register Map ..................................................................................................... 173

10.3.2

Temperature Event Status Register (TEVSTS) ......................................................... 174

10.3.3

Temperature Event to SMI Register (TEVSMI) ......................................................... 175

10.3.4

Temperature Event to IRQ Register (TEVIRQ) ......................................................... 176

10.3.5

TMS Configuration Register (TMSCFG) .................................................................... 177

10.3.6

TMS Bank Select Register (TMSBS) ......................................................................... 177

10.3.7

Temperature Channel Configuration and Status Register (TCHCFST) .................... 178

10.3.8

Read Channel Temperature Register (RDCHT) ........................................................ 179

10.3.9

Channel Temperature High Limit Register (CHTH) ................................................... 179

10.3.10 Channel Temperature Low Limit Register (CHTL) .................................................... 179

10.3.11 Channel Overtemperature Limit Register (CHOTL) .................................................. 179

10.4

TMS REGISTER BITMAP ....................................................................................................... 180

10.4.1

TMS Control and Status Registers

.......................................................................... 180

10.4.2

TMS Channel Registers ........................................................................................... 180

10.5

USAGE HINTS ........................................................................................................................ 181

10.5.1

Remote Diode Selection ............................................................................................ 181

10.5.2

ADC Noise Filtering ................................................................................................... 181

10.5.3

PC Board Layout ....................................................................................................... 181

10.5.4

Twisted Pair and Shielded Cables ............................................................................. 183

10.5.5

Obtaining the Specified VLM/TMS Accuracy ............................................................. 183

11.0

Legacy Functional Blocks

11.1

KEYBOARD AND MOUSE CONTROLLER (KBC) .................................................................. 184

11.1.1

General Description ................................................................................................... 184

11.1.2

KBC Register Map ..................................................................................................... 184

11.1.3

KBC Bitmap Summary ............................................................................................... 184

11.2

FLOPPY DISK CONTROLLER (FDC) ..................................................................................... 185

11.2.1

General Description ................................................................................................... 185

11.2.2

FDC Register Map ..................................................................................................... 185

11.2.3

FDC Bitmap Summary ............................................................................................... 186

11.3

PARALLEL PORT .................................................................................................................... 187

11.3.1

General Description ................................................................................................... 187

11.3.2

Parallel Port Register Map ......................................................................................... 187

11.3.3

Parallel Port Bitmap Summary .................................................................................. 188

11.4

UART FUNCTIONALITY (SP1 AND SP2) ............................................................................... 190

11.4.1

General Description ................................................................................................... 190

11.4.2

UART Mode Register Bank Overview ....................................................................... 190

11.4.3

SP1 and SP2 Register Maps for UART Functionality ................................................ 191

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