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TMS570LS3137 bảng dữ liệu(PDF) 87 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  TMS570LS3137 16- and 32-Bit RISC Flash Microcontroller
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SPNS162C – APRIL 2012 – REVISED APRIL 2015
Table 6-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)
NO.
PARAMETER
MIN
NOM
MAX
UNIT
3
tc(EMRCYCLE)
EMIF read cycle time (EW = 0)
(RS+RST+RH)*
(RS+RST+RH)*
(RS+RST+RH)*
ns
E -3
E
E + 3
EMIF read cycle time (EW = 1)
(RS+RST+RH+( (RS+RST+RH+( (RS+RST+RH+(
ns
EWC*16))*E -3
EWC*16))*E EWC*16))*E + 3
4
tsu(EMCEL-EMOEL)
Output setup time, EMIFnCS[4:2]
ns
(RS)*E-4
(RS)*E
(RS)*E+3
low to EMIFnOE low (SS = 0)
Output setup time, EMIFnCS[4:2]
ns
-3
0
+3
low to EMIFnOE low (SS = 1)
5
th(EMOEH-EMCEH)
Output hold time, EMIFnOE high
ns
(RH)*E -4
(RH)*E
(RH)*E + 3
to EMIFnCS[4:2] high (SS = 0)
Output hold time, EMIFnOE high
ns
-3
0
+3
to EMIFnCS[4:2] high (SS = 1)
6
tsu(EMBAV-EMOEL)
Output setup time, EMIFBA[1:0]
ns
(RS)*E-4
(RS)*E
(RS)*E+3
valid to EMIFnOE low
7
th(EMOEH-EMBAIV)
Output hold time, EMIFnOE high
ns
(RH)*E-4
(RH)*E
(RH)*E+3
to EMIFBA[1:0] invalid
8
tsu(EMAV-EMOEL)
Output setup time,
ns
EMIFADDR[21:0] valid to
(RS)*E-4
(RS)*E
(RS)*E+3
EMIFnOE low
9
th(EMOEH-EMAIV)
Output hold time, EMIFnOE high
ns
(RH)*E-4
(RH)*E
(RH)*E+3
to EMIFADDR[21:0] invalid
10
tw(EMOEL)
EMIFnOE active low width (EW
ns
(RST)*E-3
(RST)*E
(RST)*E+3
= 0)
EMIFnOE active low width (EW
(RST+(EWC*16
(RST+(EWC*16
(RST+(EWC*16
ns
= 1)
)) *E-3
))*E
)) *E+3
11
td(EMWAITH-EMOEH)
Delay time from EMIFnWAIT
ns
3E-3
4E
4E+30
deasserted to EMIFnOE high
29
tsu(EMDQMV-EMOEL)
Output setup time,
ns
EMIFnDQM[1:0] valid to
(RS)*E-4
(RS)*E
(RS)*E+3
EMIFnOE low
30
th(EMOEH-EMDQMIV)
Output hold time, EMIFnOE high
ns
(RH)*E-4
(RH)*E
(RH)*E+3
to EMIFnDQM[1:0] invalid
Writes
15
tc(EMWCYCLE)
EMIF write cycle time (EW = 0)
(WS+WST+WH) (WS+WST+WH) (WS+WST+WH)
ns
* E-3
*E
* E+3
EMIF write cycle time (EW = 1)
(WS+WST+WH
(WS+WST+WH
ns
(WS+WST+WH
+( EWC*16))*E
+( EWC*16))*E
+(E WC*16))*E
-3
+ 3
16
tsu(EMCEL-EMWEL)
Output setup time, EMIFnCS[4:2]
ns
(WS)*E -4
(WS)*E
(WS)*E + 3
low to EMIFnWE low (SS = 0)
Output setup time, EMIFnCS[4:2]
ns
-4
0
+3
low to EMIFnWE low (SS = 1)
17
th(EMWEH-EMCEH)
Output hold time, EMIFnWE high
ns
(WH)*E-4
(WH)*E
(WH)*E+3
to EMIFnCS[4:2] high (SS = 0)
Output hold time, EMIFnWE high
ns
-4
0
+3
to EMIFCS[4:2] high (SS = 1)
18
tsu(EMDQMV-EMWEL)
Output setup time, EMIFBA[1:0]
ns
(WS)*E-4
(WS)*E
(WS)*E+3
valid to EMIFnWE low
19
th(EMWEH-EMDQMIV)
Output hold time, EMIFnWE high
ns
(WH)*E-4
(WH)*E
(WH)*E+3
to EMIFBA[1:0] invalid
20
tsu(EMBAV-EMWEL)
Output setup time, EMIFBA[1:0]
ns
(WS)*E-4
(WS)*E
(WS)*E+3
valid to EMIFnWE low
21
th(EMWEH-EMBAIV)
Output hold time, EMIFnWE high
ns
(WH)*E-4
(WH)*E
(WH)*E+3
to EMIFBA[1:0] invalid
22
tsu(EMAV-EMWEL)
Output setup time,
ns
EMIFADDR[21:0] valid to
(WS)*E-4
(WS)*E
(WS)*E+3
EMIFnWE low
Copyright © 2012–2015, Texas Instruments Incorporated
System Information and Electrical Specifications
87
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