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TMS570LS3137 bảng dữ liệu(PDF) 43 Page - Texas Instruments |
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TMS570LS3137 bảng dữ liệu(HTML) 43 Page - Texas Instruments |
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43 / 173 page  Address Wait States Data Wait States RAM Address Wait States Data Wait States Flash 0MHz 0MHz 0MHz 0MHz 100MHz 0 1 3 0 0 0 150MHz 2 150MHz 1 f HCLK(max) 50MHz f HCLK(max) f HCLK(max) f HCLK(max) TMS570LS3137 www.ti.com SPNS162C – APRIL 2012 – REVISED APRIL 2015 5.5 Switching Characteristics for Clock Domains Over Recommended Operating Conditions Table 5-1. Clock Domain Timing Specifications PARAMET DESCRIPTION CONDITIONS MIN MAX UNIT ER Pipeline mode enabled 160 PGE Pipeline mode disabled 50 fHCLK HCLK - System clock frequency MHz Pipeline mode enabled 180 ZWT Pipeline mode disabled 50 fGCLK GCLK - CPU clock frequency fHCLK MHz fVCLK VCLK - Primary peripheral clock frequency 100 MHz VCLK2 - Secondary peripheral clock fVCLK2 100 MHz frequency VCLK3 - Secondary peripheral clock fVCLK3 100 MHz frequency VCLKA1 - Primary asynchronous peripheral fVCLKA1 100 MHz clock frequency VCLKA2 - Secondary asynchronous fVCLKA2 100 MHz peripheral clock frequency VCLKA4 - Secondary asynchronous fVCLKA4 50 MHz peripheral clock frequency fRTICLK RTICLK - clock frequency fVCLK MHz 5.6 Wait States Required Figure 5-1. Wait States Scheme As shown in Figure 5-1, the TCM RAM can support program and data fetches at full CPU speed without any address or data wait states required. The TCM flash can support zero address and data wait states up to a CPU speed of 50 MHz in nonpipelined mode. The flash supports a maximum CPU clock speed of 160 MHz in pipelined mode for the PGE Package and 180 MHz for the ZWT package, with one address wait state and three data wait states. The flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data wait state. Copyright © 2012–2015, Texas Instruments Incorporated Specifications 43 Submit Documentation Feedback |
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