TMS570LS3137 datasheet(86/173 Pages) TI1

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EMIF_nCS[3:2]

Asserted

EMIF_BA[1:0]

EMIF_ADDR[21:0]

EMIF_DATA[15:0]

EMIF_nWE

EMIF_WAIT

SETUP

Extended Due to EMIF_WAIT

Deasserted

STROBE

STROBE HOLD

TMS570LS3137

SPNS162C – APRIL 2012 – REVISED APRIL 2015

www.ti.com

Figure 6-14. EMIFnWAIT Write Timing Requirements

Table 6-27. EMIF Asynchronous Memory Timing Requirements

NO.

MIN

NOM

MAX

UNIT

Reads and Writes

EMIF clock period

tw(EM_WAIT)

Pulse duration, EMIFnWAIT

assertion and deassertion

Reads

tsu(EMDV-EMOEH)

Setup time, EMIFDATA[15:0]

valid before EMIFnOE high

th(EMOEH-EMDIV)

Hold time, EMIFDATA[15:0] valid

0.5

after EMIFnOE high

tsu(EMOEL-EMWAIT)

Setup Time, EMIFnWAIT

4E+30

asserted before end of Strobe

Phase(1)

Writes

tsu(EMWEL-EMWAIT)

Setup Time, EMIFnWAIT

4E+30

asserted before end of Strobe

Phase(1)

(1)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended

wait states. Figure Figure 6-12 and Figure Figure 6-14 describe EMIF transactions that include extended wait states inserted during the

STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start

of where the HOLD phase would begin if there were no extended wait cycles.

Table 6-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3)

NO.

PARAMETER

MIN

NOM

MAX

UNIT

Reads and Writes

td(TURNAROUND)

Turn around time

(TA)*E - 4

(TA)*E

(TA)*E + 3

Reads

(1)

TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,

MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle

Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–1], RH[8–1], WS[16–1], WST[64–1],

WH[8–1], and MEWC[1–256]. See the TMS570LS31X/21X Technical Reference Manual (SPNU499) for more information.

(2)

E = EMIF_CLK period in ns.

(3)

EWC = external wait cycles determined by EMIFnWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note

that the maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See

the TMS570LS31X/21X Technical Reference Manual (SPNU499) for more information.

System Information and Electrical Specifications

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