TMS570LS3137 datasheet(6/173 Pages) TI1

6 / 173 page

TMS570LS3137

SPNS162C – APRIL 2012 – REVISED APRIL 2015

www.ti.com

Table of Contents

Device Overview

......................................... 1

6.11

Tightly Coupled RAM (TCRAM) Interface Module

.. 80

1.1

Features

.............................................. 1

6.12

Parity Protection for Peripheral RAMs

.............. 80

1.2

Applications

........................................... 2

6.13

On-Chip SRAM Initialization and Testing

........... 82

1.3

Description

............................................ 3

6.14

External Memory Interface (EMIF)

.................. 84

1.4

Functional Block Diagram

............................ 5

6.15

Vectored Interrupt Manager

......................... 91

Revision History

......................................... 7

6.16

DMA Controller

...................................... 94

Device Comparison

..................................... 9

6.17

Real Time Interrupt Module

......................... 96

Terminal Configuration and Functions

........... 10

6.18

Error Signaling Module

.............................. 98

4.1

PGE QFP Package Pinout (144-Pin)

............... 10

6.19

Reset / Abort / Error Sources

...................... 102

4.2

ZWT BGA Package Ball-Map (337-Ball Grid Array)

6.20

Digital Windowed Watchdog

....................... 104

4.3

Terminal Functions

................................. 12

6.21

Debug Subsystem

................................. 105

Specifications

.......................................... 41

Peripheral Information and Electrical

Specifications

......................................... 116

5.1

Absolute Maximum Ratings

........................ 41

7.1

Peripheral Legend

................................. 116

5.2

ESD Ratings

........................................ 41

7.2

Multibuffered 12-Bit Analog-to-Digital Converter

.. 116

5.3

Power-On Hours (POH)

............................. 41

7.3

General-Purpose Input/Output

..................... 127

5.4

Recommended Operating Conditions

............... 42

7.4

Enhanced High-End Timer (N2HET)

.............. 128

5.5

Switching Characteristics for Clock Domains

....... 43

7.5

FlexRay Interface

.................................. 133

5.6

Wait States Required

............................... 43

7.6

Controller Area Network (DCAN)

.................. 135

5.7

Power Consumption

................................. 44

7.7

Local Interconnect Network Interface (LIN)

........ 136

5.8

Input/Output Electrical Characteristics

.............. 45

7.8

Serial Communication Interface (SCI)

............. 137

5.9

Thermal Resistance Characteristics

................ 46

7.9

Inter-Integrated Circuit (I2C)

....................... 138

5.10

Output Buffer Drive Strengths

...................... 47

7.10

Multibuffered / Standard Serial Peripheral

5.11

Input Timings

........................................ 48

Interface

............................................ 141

5.12

Output Timings

...................................... 48

7.11

Ethernet Media Access Controller

................. 153

5.13

Low-EMI Output Buffers

............................ 50

Device and Documentation Support

.............. 157

System Information and Electrical

8.1

Device Support

..................................... 157

Specifications

........................................... 52

8.2

Documentation Support

............................ 159

6.1

Device Power Domains

............................. 52

8.3

Community Resources

............................. 159

6.2

Voltage Monitor Characteristics

..................... 53

8.4

Trademarks

........................................ 159

6.3

Power Sequencing and Power On Reset

........... 54

8.5

Electrostatic Discharge Caution

................... 159

6.4

Warm Reset (nRST)

................................. 56

8.6

Glossary

............................................ 159

6.5

ARM-R4F CPU Information

......................... 57

8.7

Device Identification Code Register

............... 160

6.6

Clocks

............................................... 60

8.8

Die Identification Registers

....................... 161

6.7

Clock Monitoring

.................................... 68

8.9

Module Certifications

............................... 161

6.8

Glitch Filters

......................................... 70

Mechanical Packaging and Orderable

6.9

Device Memory Map

................................ 71

Information

............................................. 168

6.10

Flash Memory

....................................... 77

9.1

Packaging Information

............................. 168

Table of Contents

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