TMS320C6472ECTZ datasheet(143/269 Pages) TI1

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TMS320C6472

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SPRS612G

– JUNE 2009 – REVISED JULY 2011

– The RESETSTAT pin becomes active (low), indicating the device is in reset.

2. The RESET pin may now be released (driven inactive high). When the RESET pin is released, the

configuration pin values are latched and the PLL controllers immediately change their system clocks to

their default divide-down values. Other device initialization is also started.

3. After device initialization is complete, the RESETSTAT pin goes inactive (high).

4. The device is now out of reset, device execution begins as dictated by the selected boot mode (see

Section 2.4, Boot Mode Sequence).

NOTE

The POR pin should be held inactive (high) throughout the Warm Reset sequence.

Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met.

The RESET pin should not be tied together with the POR pin.

7.7.3

System Reset

System Reset is initiated by:

•

The emulator

•

The local watchdog timeout (when Reset mux is configured to route this as System Reset)

A System Reset maintains memory contents and does not reset the clock logic or the emulation circuitry.

The device configuration pins are also not re-latched and the state of the peripherals (enabled/disabled) is

also not affected. A System Reset is initiated by the emulator or watchdog timer. For information on how

to configure the action corresponding to a watchdog timeout, see Section 3.8.2, Reset Mux Registers.

During a System Reset, the following happens:

1. The reset is allowed to propagate through the system. Internal system clocks are not affected.

2. The PLL controllers retain their configuration. The PLLs also remain locked.

3. The RESETSTAT pin goes low to indicate an internal reset is being generated.

4. The boot sequence is started after the system clocks are re-aligned. Since the configuration pins

(including the BOOTMODE[3:0] pins) are not latched with a System Reset, the previous values, as

shown in the DEVSTAT register, are used to select the boot mode.

NOTE

A System Reset should not be used if the peripheral used for boot loading was disabled

following boot.

7.7.4

Local Reset

The Local Reset provides a local reset to the C64x+ megamodule, without destroying clock alignment or

memory contents. It does not affect any chip components. Local reset is initiated by asserting the LRESET

input (low), selecting the intended C64x+ megamodule(s) with the CORESEL[2:0] inputs, and then

latching it with the rising LRESETNMIEN input. The C64x+ megamodule(s) are held in reset until LRESET

input is latched high by the rising LRESETNMIEN input while selecting the intended C64x+ megamodule

with the CORESEL[2:0] inputs. Therefore, to assert and de-assert LRESET, two LRESETNMIEN pulses

are required where the first latches LRESET low and the second latches LRESET high. Timing

requirements for Local Reset can be found in Table 7-16 and Figure 7-12.

The external system is not notified of this reset. Once LRESET is deasserted, C64x+ megamodule goes

through a local boot sequence. In certain cases, a watchdog timeout may also cause a local reset of an

individual C64x+ megamodule. For information on how to configure the action corresponding to a

watchdog timeout, see Section 3.8.2, Reset Mux Registers.

C64x+ Peripheral Information and Electrical Specifications

143

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