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TMS320C6472ECTZ bảng dữ liệu(PDF) 81 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  TMS320C6472 Fixed-Point Digital Signal Processor
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TMS320C6472
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SPRS612G
– JUNE 2009 – REVISED JULY 2011
3.7.3
Host Interrupt and Event Pulse Generation Registers (IPCGR15 and IPCAR15)
The host interrupt and event pulse generation registers (IPCGR15 (or IPCGRH) and IPCAR15 (or
IPCARH)) facilitate host CPU interrupt. Operation and use of the IPCGR15 register is the same as
registers IPCGR0-5 and the IPCAR15 register is the same as registers IPCAR0-5. The interrupt output
pulse created by the IPCGR15 register is driven on a device pin host interrupt/event output (HOUT). The
interrupt output pulse is asserted for 4 CPU/6 cycles followed by a deassertion of 4 CPU/6 cycles.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SRCS27
SRCS26
SRCS25
SRCS24
SRCS23
SRCS22
SRCS21
SRCS20
SRCS19
SRCS18
SRCS17
SRCS16
SRCS15
SRCS14
SRCS13
SRCS12
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
15
14
13
12
11
10
9
8
7
6
5
4
3
1
0
SRCS11
SRCS10
SRCS9
SRCS8
SRCS7
SRCS6
SRCS5
SRCS4
SRCS3
SRCS2
SRCS1
SRCS0
Reserved
IPCG
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-000
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-11. IPC Generation Register (IPCGR15)
Table 3-16. IPC Generation Register (IPCGR15) Field Descriptions
Bit
Field
Value
Description
31:4
SRCS[27:0]
Write:
0
No effect
1
Set register bit
Read:
Returns current value of internal register bit
3:1
Reserved
Reserved
0
IPCG
Write:
0
No effect
1
Create an interrupt pulse on the device pin (HOUT)
Read:
Returns 0, no effect
Copyright
© 2009–2011, Texas Instruments Incorporated
Device Configuration
81
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