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TMS320C6472
www.ti.com
SPRS612G
– JUNE 2009 – REVISED JULY 2011
3.8
Timer Event Manager Registers
3.8.1
Timer Pin Manager Register (TPMGR)
The timer pin manager register (TPMGR) configures the timer output pin. The TPMGR register details are
shown in Figure 3-13 and described in Table 3-18.
31
4
3
0
Reserved
TOUTSEL
R-0000 0000 0000 0000 0000 0000 0000
R/W-0000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 3-13. Timer Pin Manager Register (TPMGR)
Table 3-18. Timer Pin Manager Register (TPMGR) Field Descriptions
Bit
Field
Value
Description
31:4
Reserved
Reserved
3:0
TOUTSEL
0000
Nothing selected for TIMO2
0001
Timer64 6 - TOUTL selected for TIMO2
0010
Timer64 6 - TOUTH selected for TIMO2
0011
Timer64 7 - TOUTL selected for TIMO2
0100
Timer64 7 - TOUTH selected for TIMO2
0101
Timer64 8 - TOUTL selected for TIMO2
0110
Timer64 8 - TOUTH selected for TIMO2
0111
Timer64 9 - TOUTL selected for TIMO2
1000
Timer64 9 - TOUTH selected for TIMO2
1001
Timer64 10 - TOUTL selected for TIMO2
1010
Timer64 10 - TOUTH selected for TIMO2
1011
Timer64 11 - TOUTL selected for TIMO2
1100
Timer64 11 - TOUTH selected for TIMO2
1101-
Reserved
1111
Copyright
© 2009–2011, Texas Instruments Incorporated
Device Configuration
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