TMS320C6472ECTZ datasheet(91/269 Pages) TI1

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TMS320C6472

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SPRS612G

– JUNE 2009 – REVISED JULY 2011

4.2

Data Switch Fabric Connections

Figure 4-1 shows the connection between slaves and masters through the data switched central resource

(SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves

via 128-bit data buses running at frequency equal to the CPU frequency divided by 3.

Some peripherals and the C64x+ megamodule have both slave and master ports. Note that each EDMA3

transfer controller has an independent connection to the data SCR.

The Serial RapidIO (SRIO) peripheral has two connections to the data SCR. The first connection is used

when descriptors are being fetched from system memory. The other connection is used for all other data

transfers.

Note that masters can access the configuration SCR through the data SCR. The configuration SCR is

described in Section 4.4. Not all masters on the C6472 DSP may connect to all slaves. Allowed

connections are summarized in Table 4-1.

System Interconnect

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