TMS320C6472ECTZ datasheet(176/269 Pages) TI1

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TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

www.ti.com

7.11 DDR2 Memory Controller

The 32-bit DDR2 Memory Controller bus of the C6472 is used to interface to JEDEC DDR2 SDRAM

devices. The DDR2 bus is designed to sustain a throughput of up to 2.13 GBps at a 533-MHz data rate

(267-MHz clock rate) as long as data requests are pending in the DDR2 Memory Controller. The DDR2

external bus only interfaces to DDR2 devices; it does not share the bus with any other types of

peripherals.

7.11.1 DDR2 Memory Controller Device-Specific Information

The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces

such as HPI and TSIP. For these other interfaces, the device timing was specified in terms of data manual

specifications and I/O buffer information specification (IBIS) models. For the C6472 DDR2 memory bus,

the approach is to specify compatible DDR2 devices and provide the printed circuit board (PCB) solution

and guidelines directly to the user. Texas Instruments (TI) has performed the simulation and system

characterization to ensure all DDR2 interface timings in this solution are met. The complete DDR2 system

solution is documented in the TMS320C6472/TMS320TCI6486 DDR2 Implementation Guidelines

application report (literature number SPRAAT7).

TI only supports designs that follow the board design guidelines outlined in the SPRAAT7

application report.

The DDR2 Memory Controller pins must be enabled by setting the DDREN configuration pin high during

device reset. The DDREN pin must remain high at all times if the DDR2 Memory Controller is enabled. If

DDREN is low, all data accessed destined for the DDR2 will be NULL terminated at the SCR. For more

details, see Section 3.1, Device Configuration at Device Reset. The DDR2 Memory Controller on the

TMS320C6472 device supports the following memory topologies:

•

A 32-bit wide configuration interfacing to two 16-bit wide DDR2 SDRAM devices.

•

A 16-bit wide configuration interfacing to a single 16-bit wide DDR2 SDRAM device.

7.11.2 DDR2 Memory Controller Peripheral Register Descriptions

Table 7-49. DDR2 Memory Controller Registers

HEX ADDRESS RANGE

ACRONYM

7800 0000

MIDR

DDR2 Memory Controller Module and Revision Register

7800 0004

DMCSTAT

DDR2 Memory Controller Status Register

7800 0008

SDCFG

DDR2 Memory Controller SDRAM Configuration Register

7800 000C

SDRFC

DDR2 Memory Controller SDRAM Refresh Control Register

7800 0010

SDTIM1

DDR2 Memory Controller SDRAM Timing 1 Register

7800 0014

SDTIM2

DDR2 Memory Controller SDRAM Timing 2 Register

7800 0018

Reserved

7800 0020

BPRIO

DDR2 Memory Controller Burst Priority Register

7800 0024 - 7800 00E0

Reserved

7800 00E4

DMCCTL

DDR2 Memory Controller Control Register

7800 00E8 - 7FFF FFC

Reserved

176

C64x+ Peripheral Information and Electrical Specifications

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